BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_01
2. 5 Malfunction when VDD falls
As seen in Figure 29, note that if the VDD pin voltage (VDD) drops steeply below 1.2 V when −VDET < VSENSE
+VDET, erroneous detection may occur.
<
When VDD_Low ≥ 1.2 V, erroneous detection does not occur.
When VDD_Low < 1.2 V, the more the VDD falling amplitude increases or the shorter the falling time becomes, the
easier the erroneous detection.
Perform thorough evaluation in actual application.
VDD_High
VDD
VDD_Low (Voltage drops below 1.2 V.)
+VDET
VSENSE
−VDET
VOUT falling influenced by VDD falling
(erroneous detection)
VOUT
Figure 29
The S-1004Cx50 example in Figure 30 shows an example of erroneous detection boundary conditions.
12
10
8
6
4
2
0
Danger of erroneous
detection
0.1
1
10
100
1000
t
F
[s]
Figure 30
Remark Test conditions
Product name: S-1004Cx50
VSENSE −VDET(S) + 0.1 V
VDD_High
VDD_Low
:
:
:
VDD pin voltage before falling
VDD pin voltage after falling (0.95 V)
VDD_High − VDD_Low
ΔVDD
:
tF:
Falling time of VDD from VDD_High − ΔVDD × 10% to VDD_Low + ΔVDD × 10%
V
V
DD_High
DD_High VDD 10%
VDD
VDD_Low VDD 10%
V
DD_Low
t
F
Figure 31
20
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