VOLTAGE DETECTOR WITH SENSE PIN
S-1002 Series
Rev.1.1_02
1. 2 S-1002 Series CA / CB type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (+VDET) or higher, the Nch transistor is turned off and the Pch transistor is turned
on to output VDD ("H"). Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB + RC ) • VSENSE
.
RA + RB + RC
(2) Even if VSENSE decreases to +VDET or lower, VDD is output when VSENSE is higher than the detection voltage
(−VDET).
When VSENSE decreases to −VDET or lower (point A in Figure 24), the Nch transistor is turned on and the Pch
transistor is turned off. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time
(tDET).
RB • VSENSE
RA + RB
At this time, N1 is turned on, and the input voltage to the comparator is
.
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds −VDET, VSS is output when VSENSE is lower than +VDET
.
(5) When VSENSE increases to +VDET or higher (point B in Figure 24), the Nch transistor is turned off and the Pch
transistor is turned on. And then VDD is output from the OUT pin after the elapse of the release delay time
(tRESET).
SENSE
VDD
Pch
RA
*1
VDD
+
−
OUT
*1
*1
VSENSE
RB
*1
VREF
+
N1
Nch
V
RC
VSS
*1. Parasitic diode
Figure 23 Operation of S-1002 Series CA / CB Type
(2) (3) (4) (5)
(1)
B
Hysteresis width
(VHYS
Release voltage (+VDET
Detection voltage (−VDET
)
A
)
)
VSENSE
Minimum operation voltage
VSS
VDD
VSS
Output from OUT pin
tDET
tRESET
Figure 24 Timing Chart of S-1002 Series CA / CB Type
17
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