SAB 82525
SAB 82526
SAF 82525
SAF 82526
Examples
The interaction between the HSCX and the CPU during the transmission and reception of
I-frames is illustrated in figure 12, the flow control with RR/RNR during the reception of
I-frames in figure 13, and during the transmission of I-frames in figure 14. Both the sequence
of the poll cycle and protocol errors are illustrated in figure 15.
XPR
(0.0)
Ι
RR (1)
Ι
Transmit Frame
ALLS
WFA
(0.1)
Ι
RME
RR (1)
Reception Ι Frame
XPR
(1.1)
(1.2)
Ι
Ι
Ι
Transmit Frame
Ι
Confirm with Frame
ALLS
RME
WFA
RR (2)
ITD00232
Figure 12
Transmission/Reception I-Frames
RNR
(0.0)
Ι
RNR (0)
RR (0) p = 1
RR (0) f = 1
RR (0) p = 1
RR (0) f = 1
XRNR
RR
(0.0)
Ι
RME
RR (1)
ITD00234
Figure 13
Flow Control/Reception
Semiconductor Group
32
SIEMENS [ Siemens Semiconductor Group ]
