SAB
SAB
SAF
SAF
3.3 Error Handling
Depending on the error type, erroneous frames are handled according
table 1.
Table 1
Error Handling
Frame Type
I
Error Type
CRC error
aborted
unexpec. N(S)
unexpec. N(R)
CRC error
aborted
unexpec. N(R)
with I-field
Generated
Response
–
–
S-frame
–
–
–
–
–
Generated
Interrupt
RME
RME
–
PCE
–
–
PCE
PCE
82525
82526
82525
82526
Rec. Status
CRC error
abort
–
–
–
S
Note:
The station variables (V(S), V(R)) are not changed.
4
CPU Interface
4.1 Register Set
The communication between the CPU and the HSCX is done via a set of directly accessible
8-bit registers. The CPU sets the operating modes, controls function sequences, and gets
status information by writing or reading these registers (Command/Status transfer). Complete
information concerning the register functions is provided in detailed register description. The
most important functions programmable via these registers are:
– setting of operating and clocking modes
– layer-2 functions
– data transfer modes (Interrupt, DMA)
– bus mode
– DPLL mode
– baudrate generator
– test loop
Each of two serial channels of HSCX is controlled via an equal, but totally independent register
file (channel A and channel B).
4.2 Data Transfer Modes
Data transfer between the system memory and the HSCX for both transmit and receive
direction is controlled by either interrupts (Interrupt Mode), or independently from CPU
interaction using the HSCX’s 4-channel DMA interface (DMA Mode).
After RESET, the HSCX operates in Interrupt Mode, where data transfer must be done by the
CPU. The user selects the DMA Mode by setting the DMA bit in the XBCH register. Both
channels can be independently operated in either Interrupt or DMA Mode (e.g. Channel
A-DMA, Channel B-Interrupt).
Semiconductor Group
38
SIEMENS [ Siemens Semiconductor Group ]
