SAB 82525
SAB 82526
SAF 82525
SAF 82526
Mode Register (READ/WRITE)
Value after RESET: 00
7
H
0
MODE
MDS1 MDS0 ADM
TMD
RAC
RTS
TRS
TLP
(22/62)
MDS1, MDS0 … Mode Select
The operating mode of the HDLC controller is selected.
00 … auto-mode
01 … non-auto mode
10 … transparent mode
11 … extended transparent mode
ADM … Address Mode
The meaning of this bit varies depending on the selected operating mode:
Auto-mode, non-auto mode
Defines the length of the HDLC address field.
0 … 8-bit address field
1 … 16-bit address field
In transparent modes, this bit differentiates between two sub-modes:
Transparent mode
0 … transparent mode 0; no address recognition.
1 … transparent mode 1; high byte address recognition.
Extended transparent mode; without HDLC framing.
0 … extended transparent mode 0; received data in RAL1.
1 … extended transparent mode 1; received data in RFIFO and RAL1.
Note: In extended transparent modes, the RAC bit must set to "0" to enable fully transparent
reception!
Semiconductor Group
89
SIEMENS [ Siemens Semiconductor Group ]
