SAB 82525
SAB 82526
SAF 82525
SAF 82526
Command Register (WRITE)
Value after RESET: 00
7
H
0
CMDR
RMC
RHR
RNR
STI
XTF
XIF
XME XRES
(21/61)
XREP
Note: The maximum time between writing to the CMDR register and the execution of the
command is 2.5 clock cycles. Therefore, if the CPU operates with a very high clock in
comparison with the HSCX’s clock, it's recommended that the CEC bit of the STAR
register is checked before writing to the CMDR register to avoid any loss of commands.
RMC … Receive Message Complete
Confirmation from CPU to HSCX, that the actual frame or data block has been fetched
following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released.
Note: In DMA mode, this command is only issued once after a RME interrupt. The HSCX does
not generate further DMA requests prior to the reception of this command.
RHR … Reset HDLC Receiver
All data in the RFIFO and the HDLC receiver deleted.
In auto-mode, additionally the transmit and receive sequence number counters are reset.
RNR/XREP … Receiver Not Ready/Transmission Repeat
The function of this command depends on the selected operation mode (MDS1, MDS0,
ADM bit in MODE):
Auto-mode: RNR
The status of the HSCX receiver is set. Determines, whether a received frame is
acknowledged via an RR, or RNR supervisory frame in auto-mode.
0 … Receiver Ready (RR)
1 … Receiver Not Ready (RNR)
Extended transparent mode 0, 1 : XREP
Together with XTF and XME set (write 2 A to CMDR), the HSCX repeatedly transmits the
H
contents of the XFIFO (1 … 32 bytes) without HDLC framing fully transparent, i.e. without
FLAG, CRC insertion, bit stuffing.
The cyclic transmission is stopped with an XRES command!
Semiconductor Group
87
SIEMENS [ Siemens Semiconductor Group ]
