SAB 82525
SAB 82526
SAF 82525
SAF 82526
8
Detailed Register Description
8.1 Register Address Arrangement
Table 11
Layout of Register Addresses
ADDRESS
Channel
REGISTER
Refer
to
page:
A
B
Read Write
00
40
:
:
:
:
RFIFO XFIFO Receive/Transmit FIFO
73 74
1F
20
21
22
23
24
25
26
27
28
29
5F
60
61
62
63
64
65
66
67
68
69
ISTA
MASK Interrupt STAtus/Mask
75 76
79 80
82
STAR CMDR STAtus/CoManD
MODE
TIMR
MODE
TIMer
84
EXIR XAD1 EXtended Interrupt/Transmit ADdress 1
RBCL XAD2 Receive Byte Count Low/Transmit ADdress 2
RAH1 Receive Address High 1
RSTA RAH2 Receive STAtus/Rec. Addr. High 2
RAL1 RAL1 Receive Address Low 1
RHCR RAL2 Receive HDLC Control/Receive Addr. Low 2
85 85
86 86
– 87
–
87 87
90
91 90
2A
2B
2C
2D
2E
2F
30
31
32
33
6A
6B
6C
6D
6E
6F
70
71
72
73
–
–
XBCL Transmit Byte Count Low
–
–
92
92
BGR
CCR2
Baudrate Generator Register
Channel Configuration Register 2
93
96 95
VSTR RLCR Version STatus/Receive Frame Length Check 96 97
CCR1 Channel Configuration Register 1 97
99
RBCH XBCH Receive/Transmit Byte Count High
–
–
–
–
TSAX Time-Slot Assignment Transmit
TSAR Time-Slot Assignment Receive
XCCR Transmit Channel Capacity
RCCR Receive Channel Capacity
–
–
–
–
99
99
99
Note: Channel A is not implemented in SAB 82526
Semiconductor Group
79
SIEMENS [ Siemens Semiconductor Group ]
