SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following figure gives an example of an interrupt controlled reception sequence, supposed
that a long frame (66 bytes) followed by two short frames (6 bytes each) are received.
Receive Frame 1(66 Bytes)
32
32
2
6
6
Serial
Interface
HSCX
CPU
Interface
. . .
. . .
...
...
...
RD
32 Bytes
RD
32 Bytes
RPF
RMC RPF
RMC RME
RMC RME
RMC RME
RMC
ITD00251
Figure 37
Interrupt Driven Reception Sequence Example
DMA Mode
If the RFIFO contains 32 bytes, the HSCX autonomously requests a block data transfer by
DMA activating the DRQR line as long as the start of the 32nd read cycle. This forces the DMA
controller to continuously perform bus cycles till 32 bytes are transferred from the HSCX to the
system memory.
If the RFIFO contains less than 32 bytes (one short frame or the last part of a long frame) the
HSCX requests a block data transfer depending on the contents of the RFIFO according to the
following table:
RFIFO
DMA
Contents
(Bytes)
Request
(Bytes)
1, 2, 3
4 - 7
4
8
8 - 15
16 - 32
16
32
Note: All available status informations after RME are summarized in table 10.
Semiconductor Group
77
SIEMENS [ Siemens Semiconductor Group ]
