SX1232
WIRELESS & SENSING
DATASHEET
T
defines the maximum duration the chip stays in Receive mode as long as no Preamble is detected. In order to
Timer2
optimize power consumption, Timer2 must be set just long enough for Preamble detection.
T
+ T defines the cycling period, i.e. time between two Preamble polling starts. In order to optimize average
Timer1
Timer2
power consumption, Timer1 should be relatively long. However, increasing Timer1 also extends packet reception duration.
In order to insure packet detection and optimize the receiver's power consumption, the received packet Preamble should
be as long as T
+ 2 x T
.
Timer1
Timer2
An example of DIO configuration for this mode is described in the following table:
Table 34 Listen Mode with PreambleDetect Condition Recommended DIO Mapping
DIO
0
Value
01
Description
CrcOk
1
3
00
00
FifoLevel
FifoEmpty
4
11
PreambleDetect – Note: MapPreambleDetect bit should be set.
7.4.2. Wake on SyncAddress Interrupt
In another possible scenario, the sequencer polls for a Preamble detection and then for a valid SyncAddress interrupt. If
events occur, the sequencer is switched off and the circuit stays in Receive mode until the user switches modes.
Otherwise, the receiver is switched off until the next Rx period.
7.4.2.1. Timing Diagram
Most of the sequencer running time is spent while no wanted signal is received. As shown by the timing diagram in
Figure 47, the circuit wakes periodically for a short time, defined by RxTimeout. The circuit is in a Low Power mode for the
rest of Timer1 + Timer2 (i.e. Timer1 + Timer2 - TrxTimeout)
No wanted signal
Idle
Receive
Idle ( Sleep + RC )
Receive
Idle
Timer2
Timer2
Timer1
Timer1
Timer1
RxTimeout
RxTimeout
Figure 47. Listen Mode with no SyncAddress Detected
If a preamble is detected before RxTimeout timer ends, the circuit stays in Receive mode and waits for a valid
SyncAddress detection. If none is detected by the end of Timer2, Receive mode is deactivated and the polling cycle
resumes, without any user intervention.
Rev 3 - August 2012
Page 87
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