SC1480
POWER MANAGEMENT
Applications Information (Cont.)
TJ − TA 150 − 85
performance, use the slowest on-time setting of 200kHz.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on
and off times. The IC duty-factor limitation is given by:
PT =
=
= 1.3W
θJA
50
Each FET must not exceed 1.3W of power dissipation.
T
ON
( )
MIN
MOSFET Power Dissipation
DUTY =
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
conduction power dissipation occurs at minimum battery
voltage:
TON(
MIN)+TOFF
(MAX
)
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
V
OUT
PDUC
=
•
2•RDS(ON)
ILOAD
VIN( )
MIN
Layout Guidelines
As with any high frequency switching regulator, it is
advisable to practice a careful layout strategy. This
includes keeping loop area as small as possible. And
properly decoupling lines that pull large currents in short
periods of time. To keep loop area small always use a
ground plane and if possible split the plane in two areas,
signal GND and power GND, then tie the two together at
one point. Be sure that high current paths have low
inductance by making trace widths wide where possible.
The SC1480 pin-outs contain digital signals on the right
and analog signals on the left side of the device. This
facilitates the isolation of digital and analog signals
enabling effective layout of the device. In summary follow
these guidelines for good PC board layout::
Typically, a small high-side MOSFET is selected to reduce
switching losses at high input voltages. However, the
RDS(ON) limits how small the MOSFET can be.
Another element of loss in the upper MOSFET is the
switching loss, especially at high input voltages, those
seen when the AC adaptor is applied. The upper MOSFET
switching losses can be estimated as follows:
CRSS
•
2• f•ILOAD
V
IN(MAX)
PDUS
=
I
GATE
Where CRSS is the reverse transfer capacitance of the
upper MOSFET and IGATE is the peak gate-drive source/
sink current which is approximately 1A for the SC1480.
• Keep high-current paths short, especially at the ground
terminals.
For the low-side MOSFET the there are only conduction
loses to be concerned about since the commutation diode
is active while the lower MOSFET switches. The worst-
case power dissipation occurs at maximum battery
voltage:
• Tie AGND and PGND together close to the IC.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using thick
copper PC boards (2oz vs 1oz) can enhance full-load
efficiency by 1% or more.
• Connect the ILIMIT resistor as close to the lower
MOSFET drain as possible, and keep the resistance
distance from the ILIM pin to the drain short. This will
improve current limit accuracy.
V
OUT
P
DLC = 1-
•
2•RDS(ON)
I
LOAD
V
IN(
MAX
)
Adding up the power dissipation for each MOSFET can
now proceed and the total for each MOSFET should not
exceed 1.3W which was calculated earlier to be the
maximum power dissipation under worst-case conditions.
1480 System DC Accuracy
Two IC parameters effect system DC accuracy, the error
comparator offset voltage, and the switching frequency
variation with line and load. The 1480 regulates to the
REFOUT voltage not the REFIN voltage. Since DDR
specifications are written with respect to REFOUT, the
offset of the reference buffer does not create a regulation
error.
Dropout Performance
The output voltage adjust range for continuous-
conduction operation is limited by the fixed 500nS
(maximum) minimum off-time one-shot. For best dropout
2006 Semtech Corp.
12
www.semtech.com
SEMTECH [ SEMTECH CORPORATION ]
