E0C88112
q
SVD Circuit
Characteristic
SVD voltage
(Unless otherwise specified: V
DD
= 1.8 to 5.5V, V
SS
= 0V, Ta = 25°C)
Symbol
Condition
Min.
Typ.
Max.
Unit Note
V
SVD
Level 1
→
Level 0
1.82
V
Level 2
→
Level 1
2.00
V
Level 3
→
Level 2
2.18
V
Level 4
→
Level 3
2.36
V
Level 5
→
Level 4
Typ×0.92 2.54 Typ×1.08
V
Level 6
→
Level 5
2.72
V
Level 7
→
Level 6
2.90
V
Level 8
→
Level 7
3.08
V
Level 9
→
Level 8
3.26
V
Level 10
→
Level 9
3.45
V
Level 11
→
Level 10
3.65
V
Level 12
→
Level 11
3.85
V
Typ×0.88
Typ×1.12
Level 13
→
Level 12
4.05
V
Level 14
→
Level 13
4.25
V
Level 15
→
Level 14
4.50
V
q
Analog Comparator Circuit
(Unless otherwise specified: V
DD
= 1.8 to 5.5V, V
SS
= 0V, Ta = 25°C)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit Note
Analog comparator
V
CMIP
Non-inverted input (CMPP)
6
0.7
V
DD
- 0.7
V
operating voltage input range
6
0.7
V
DD
- 0.7
V
V
CMIM
Inverted input (CMPM)
Analog comparator offset voltage
6
V
CMOF
V
CMIP
= 0.7V to V
DD
- 0.7V
20
mV
V
CMIM
= 0.7V to V
DD
- 0.7V
Analog comparator stability time
7
1
mS
t
CMP1
Analog comparator response time
6
2
mS
t
CMP2
V
CMIP
= 0.7V to V
DD
- 0.7V
8
V
CMIM
= 0.7V to V
DD
- 0.7V
V
CMIP
= V
CMIM
± 0.025V
Note) 6 When "without pull-up resistor" (comparator input terminal) is selected by mask option.
7 Stability time is the time from turning the circuit ON until the circuit is stabilized.
8 Response time is the time that the output result responds to the input signal.
q
Current Consumption
(Unless otherwise specified: V
DD
= Within the operating voltage in each operating mode, V
SS
= 0V, Ta = 25°C,
OSC1 = 32.768kHz crystal oscillation, C
G
= 10pF, OSC3 = External clock input, Non heavy load protection mode, C1 = 0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit Note
I
DD1
In SLEEP status
*
1
0.3
1
µA
In HALT status
2
5
µA
I
DD2
*
2
3
CPU is in operating (32.768kHz)
14
18
µA
I
DD3
*
CPU is in operating (1MHz)
0.45
0.60
mA
I
DD4
*
4
9
In heavy load protection mode
25
50
µA
I
HVL
Power current
In SLEEP status
0.2
1
µA
I
DD1
*
1
(Low power mode)
In HALT status
1
5
µA
I
DD2
*
2
CPU is in operating (32.768kHz)
8
12
µA
I
DD3
*
3
9
In heavy load protection mode
15
30
µA
I
HVL
Power current
In SLEEP status
1
3
µA
I
DD1
*
1
(High speed mode)
In HALT status
5
10
µA
I
DD2
*
2
CPU is in operating (32.768kHz)
24
30
µA
I
DD3
*
3
CPU is in operating (1MHz)
0.70
1.00
mA
I
DD4
*
4
9
In heavy load protection mode
35
70
µA
I
HVL
SVD circuit current
10
30
60
µA
I
SVDN
V
DD
= 3.0V
9
25
75
µA
I
SVDH
In heavy load protection mode
Analog comparator circuit current
40
100
µA
I
CMP1
CMPXDT = "1"
4
10
µA
I
CMP2
CMPXDT = "0"
OSC1 CR oscillation current
11
20
50
µA
I
CR1
∗1
OSC1: Stop,
OSC3: Stop,
CPU, ROM, RAM: SLEEP status,
Clock timer: Stop,
Others: Stop status
∗2
OSC1: Oscillating, OSC3: Stop,
CPU, ROM, RAM: HALT status,
Clock timer: Operating, Others: Stop status
∗3
OSC1: Oscillating, OSC3: Stop,
CPU, ROM, RAM: Operating in 32.768kHz, Clock timer: Operating, Others: Stop status
∗4
OSC1: Oscillating, OSC3: Oscillating, CPU, ROM, RAM: Operating in 1MHz,
Clock timer: Operating, Others: Stop status
Note) 9 It is the value of current which flows in the heavy load protection circuit when in the heavy load protection mode (OSC3 ON or buzzer ON).
10 The value in
x
V can be found by the following expression:
I
SVDN
(V
DD
=
x
V) = (x
×
20) - 30 (Typ. value), I
SVDN
(V
DD
=
x
V) = (x
×
30) - 30 (Max. value)
11 When OSC1 CR oscillation circuit is selected by the mask option.
Power current
(Normal mode)
5
SEIKO [ SEIKO EPSON CORPORATION ]
