E0C88112
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
QFP15-100pin
75
76
100
1
N.C.
1
26
N.C.
51
N.C.
76
N.C.
N.C.
2
27
N.C.
52
N.C.
77
N.C.
N.C.
3
28
R00/A0
53
R24/WR
78
N.C.
RESET
4
29
R01/A1
54
R25
79
R50/BZ
51
N.C.
5
30
R02/A2
55
R26
80
R51/BACK
K11/BREQ
31
R03/A3
6
56
R27/TOUT
81
P17/CMPM1
50
K10/EVIN
7
32
R04/A4
57
R30/CE0
82
P16/CMPP1
K07
8
33
R05/A5
58
R31/CE1
83
P15/CMPM0
K06
9
34
R06/A6
59
R32/CE2
84
P14/CMPP0
10
K05
35
R07/A7
60
R33/CE3
85
P13/SRDY
11
K04
36
R10/A8
61
R34/FOUT
86
P12/SCLK
12
K03
37
R11/A9
62
R35
87
P11/SOUT
E0C88112
13
K02
38
R12/A10
63
R36
88
P10/SIN
14
K01
39
R13/A11
64
R37
89
P07/D7
15
K00
40
R14/A12
65
∗
90
P06/D6
16
MCU/MPU
41
R15/A13
66
∗
91
P05/D5
INDEX
17
V
DD
42
R16/A14
67
∗
92
P04/D4
18
OSC4
43
R17/A15
68
∗
93
P03/D3
26
19
OSC3
44
R20/A16
69
∗
94
P02/D2
20
V
D1
45
R21/A17
70
∗
95
P01/D1
21
OSC2
46
R22/A18
71
∗
96
P00/D0
25
22
OSC1
47
R23/RD
72
∗
97
N.C.
23
V
SS
48
N.C.
73
N.C.
98
TEST
24
N.C.
49
N.C.
74
N.C.
99
N.C.
25
N.C.
50
N.C.
75
N.C.
100
N.C.
∗
Pins No. 65 to 72 are the pads used for outgoing inspection of the IC. Do not connect anything to these pins.
N.C. : No Connection
s
PIN DESCRIPTION
Pin name
V
DD
V
SS
V
D1
OSC1
OSC2
OSC3
OSC4
MCU/MPU
K00–K07
K10/EVIN
K11/BREQ
R00–R07/A0–A7
R10–R17/A8–A15
R20–R22/A16–A18
R23/RD
R24/WR
R25
R26
R27/TOUT
Pin No.
QFP14-80 QFP15-100
In/Out
–
–
–
I
O
I
O
I
I
I
I
O
O
O
O
O
O
O
O
Function
Power supply (+) terminal
Power supply (GND) terminal
Regulated voltage output terminal for oscillators
OSC1 oscillation input terminal
(crystal oscillation/CR oscillation/external clock input, mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal
(crystal/ceramic/CR oscillation/external clock input, mask option)
OSC3 oscillation output terminal
Terminal for setting MCU or MPU modes
Input port (K00–K07) terminal
Input port (K10) terminal or event counter external clock (EVIN) input terminal
Input port (K11) terminal or bus request signal (BREQ) input terminal
Output port (R00–R07) terminals or address bus (A0–A7)
Output port (R10–R17) terminals or address bus (A8–A15)
Output port (R20–R22) terminals or address bus (A16–A18)
Output port (R23) terminal or read signal (RD) output terminal
Output port (R24) terminal or write signal (WR) output terminal
Output port (R25) terminal
Output port (R26) terminal
Output port (R27) terminal
or programmable timer underflow signal (TOUT) output terminal
57–60
O
R30–R33/CE0–CE3 25–28
Output port (R30–R33) terminals or chip enable (CE0–CE3) output terminals
29
61
O
R34/FOUT
Output port (R34) terminal or clock (FOUT) output terminal
30–32
62–64
O
R35–R37
Output port (R35–R37) terminal
41
79
O
R50/BZ
Output port (R50) terminal or buzzer (BZ) output terminal
42
80
O
R51/BACK
Output port (R51) terminal or bus acknowledge signal (BACK) output terminal
58–51
96–89
I/O I/O port (P00–P07) terminals or data bus (D0–D7)
P00–P07/D0–D7
50
88
I/O I/O port (P10) terminal or serial I/F data input (SIN) terminal
P10/SIN
49
87
I/O I/O port (P11) terminal or serial I/F data output (SOUT) terminal
P11/SOUT
48
86
I/O I/O port (P12) terminal or serial I/F clock (SCLK) I/O terminal
P12/SCLK
47
85
I/O I/O port (P13) terminal or serial I/F ready signal (SRDY) output terminal
P13/SRDY
46
84
I/O I/O port (P14) terminal or comparator 0 non-inverted input terminal
P14/CMPP0
45
83
I/O I/O port (P15) terminal or comparator 0 inverted input terminal
P15/CMPM0
44
82
I/O I/O port (P16) terminal or comparator 1 non-inverted input terminal
P16/CMPP1
43
81
I/O I/O port (P17) terminal or comparator 1 inverted input terminal
P17/CMPM1
61
4
I
RESET
Initial reset input terminal
60
98
I
TEST
∗
Test input terminal
∗
TEST is the terminal used for outgoing inspection of the IC. For normal operation be sure it is connected to V
DD
.
74
80
77
79
78
76
75
73
72–65
64
63
1–8
9–16
17–19
20
21
22
23
24
17
23
20
22
21
19
18
16
15–8
7
6
28–35
36–43
44–46
47
53
54
55
56
3
SEIKO [ SEIKO EPSON CORPORATION ]
