E0C6S48
■ PIN CONFIGURATION
No. Pin name No. Pin name No. Pin name No. Pin name No. Pin name
QFP8-144pin
1
2
3
4
5
6
7
8
9
CB
CA
N.C.
COM0
COM1
COM2
COM3
COM4
COM5
30 SEG41
31 SEG40
32 SEG39
33 SEG38
34 SEG37
35 N.C.
59 SEG15
60 SEG14
61 SEG13
62 SEG12
63 SEG11
64 SEG10
65 SEG9
66 SEG8
67 SEG7
68 SEG6
69 SEG5
70 SEG4
71 SEG3
72 SEG2
73 SEG1
74 SEG0
75 N.C.
76 SCLK
77 SOUT
78 SIN
79 K13
80 K12
81 K11
82 K10
83 K03
84 N.C.
88 P33
89 P32
90 P31
91 P30
92 P23
93 P22
94 P21
95 P20
96 P13
97 N.C.
98 P12
99 P11
100 P10
101 P03
102 P02
103 P01
104 P00
105 R43
106 R42
107 R41
108 R40
109 R33
110 R32
111 R31
112 R30
113 R23
114 R22
115 R21
116 R20
117 R13
118 R12
119 R11
120 R10
121 R03
122 R02
123 R01
124 R00
108
73
109
72
36 N.C.
37 SEG36
38 SEG35
39 SEG34
40 SEG33
41 SEG32
42 SEG31
43 SEG30
44 SEG29
45 SEG28
46 SEG27
47 SEG26
48 SEG25
49 SEG24
50 N.C.
51 SEG23
52 SEG22
53 SEG21
54 SEG20
55 SEG19
56 SEG18
57 SEG17
58 SEG16
125
VSS
10 COM6
11 COM7
12 COM8
13 COM9
14 COM10
15 COM11
16 COM12
17 COM13
18 COM14
19 N.C.
20 COM15
21 SEG50
22 SEG49
23 SEG48
24 SEG47
25 SEG46
26 SEG45
27 SEG44
28 SEG43
29 SEG42
126 RESET
127 TEST
128 OSC4
129 OSC3
E0C6S48
130
VS1
131 OSC2
132 OSC1
133 N.C.
INDEX
144
37
134
135
136
137
138
139
140
V
V
V
V
V
V
V
DD
REF
L1
1
36
L2
L3
L4
L5
141 CF
142 CE
143 CD
144 CC
85 K02
86 K01
87 K00
■ PIN DESCRIPTION
N.C. = No Connection
Pin name
Pin No.
134
125
I/O
–
–
Function
V
V
V
V
DD
SS
S1
Power supply (+)
Power supply (-)
130
136–140
–
–
Internal logic system/oscillation system regulated voltage output
L1–VL5
LCD system power supply
1/4 bias generated internally, 1/5 bias generated externally
LCD system power test pin
1
2
V
REF
135
2, 1, 144–141
132
O
–
I
CA–CF
OSC1
LCD system voltage booster condenser connecting pin
1
Crystal or CR oscillator input
OSC2
OSC3
OSC4
COM0–COM15
SEG0–SEG50
131
129
128
O
I
O
O
O
Crystal or CR oscillator output 1, C
D
buiil-in
1
CR or ceramic oscillator input
CR or ceramic oscillator output
1
4–18, 20
74–51, 49–37,
34–21
87–85, 83
82–79
104–101
100–98, 96
95–92
91–88
124–121
120–117
116–113
112–110
109
LCD common output (1/8 duty or 1/16 duty is selected on software)
LCD segment output
1
K00–K03
K10–K13
P00–P03
P10–P13
P20–P23
P30–P33
R00–R03
R10–R13
R20–R23
R30–R32
R33
R40
R41
R42
R43
SIN
SOUT
I
I
Input port (pull up resistor is available by mask option)
Input port (pull up resistor is available by mask option)
1
Complementary output or
Nch open drain output
1
I/O I/O port
I/O I/O port
I/O I/O port
I/O I/O port or output port
1
O
O
O
O
O
O
O
O
O
I
Output port
Output port
Output port
Output port
1
Output port, SRDY output or PTCLK output
1
108
107
106
105
78
77
Output port or FOUT output
Output port
Output port, BZ output or FOUT output
1
1
Output port or BZ output
Serial interface data input
Serial interface data output
O
SCLK
76
I/O Serial interface clock input/output
RESET
TEST
126
127
I
I
Initial reset input terminal
Testing input terminal
3
1 Selected by mask option
2 Leave the VREF pin unconnected (N.C.).
3 The TEST pin is used when the IC load is being detected. During ordinary operation be certain to connect this pin to VDD
.
3
SEIKO [ SEIKO EPSON CORPORATION ]
