E0C63B07
q
Timing Chart
Initial reset
Supply voltage
OSC1 oscillation clock
Oscillation detection
circuit output
(High Active)
Oscillation is in unstabilized state
3 sec
(Note)
(Note) f
OSC1
=32.768 kHz : 6 msec min.
f
OSC1
=76.8 kHz : 3 msec min.
f
OSC1
=153.6 kHz : 1.5 msec min.
RESET terminal
(Low Active)
Internal reset signal
(High Active)
System clock switching
∗
1 instruction execution time or longer
∗
DBON
(Note)
100 msec min.
∗
∗
∗
VDSEL
(Note)
∗
VDC
2.5 msec min.
OSCC
5 msec min.
CLKCHG
(Note) Use DBON and VDSEL only when changes are requied.
Supply voltage doubler control during heavy load driving
∗
1 instruction execution time or longer
DBON
100 msec min.
∗
∗
VDSEL
100 msec min.
VCSEL
(Note)
1 msec min.
ON
Heavy load
OFF
(Note) VCSEL is used only when it is required.
2 sec min.
10
SEIKO [ SEIKO EPSON CORPORATION ]
