E0C63158
q
Timing Chart
Reset
Supply voltage
OSC1 oscillation clock
Oscillation unstabilized state
3 sec
6 msec min.
(f
OSC1
= 32.768 kHz)
RESET terminal
(active-Low)
Internal reset signal
(active-High)
System clock switching
∗
1 instruction execution time or longer
VDC
2.5 msec min.
∗
OSCC
5 msec min.
CLKCHG
(Note) When the OSC1 oscillation circuit has been selected as the CR oscillation circuit,
it is not necessary to set the VDC register.
Whether the VDC register value is "1" or "0" does not matter.
Supply voltage V
C2
mode control during heavy load driving
∗
1 instruction execution time or longer
DBON
100 msec min.
∗
∗
VDSEL
100 msec min.
VADSEL
(Note)
1 msec min.
ON
Heavy load
OFF
(Note) VADSEL is used only when it is required.
2 sec min.
9
SEIKO [ SEIKO EPSON CORPORATION ]
