E0C63158
QFP13-64pin
48
33
49
32
E0C63158
INDEX
64
17
1
16
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin name
V
SS
OSC1
OSC2
V
D1
OSC3
OSC4
V
DD
RESET
TEST
AV
DD
AV
SS
AV
REF
CB
CA
V
C2
N.C.
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
P43
P42
P41
P40
P33
P32
P31
P30
P23
P22
P21
P20
P13
P12
P11
P10
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name No. Pin name
P03
49 N.C.
P02
50 N.C.
P01
51 N.C.
P00
52 R01
R23
53 R00
R22
54 BZ
R21
55 K00
R20
56 K01
R13
57 K02
R12
58 K03
R11
59 K10
R10
60 K11
R03
61 K12
R02
62 K13
N.C.
63 K20
N.C.
64 N.C.
N.C. : No Connection
s
PIN DESCRIPTION
Pin name
V
DD
V
SS
V
D1
V
C2
CA, CB
OSC1
OSC2
OSC3
OSC4
K00–K03
K10–K13
K20
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
R00
R01
R02
R03
R10–R13
R20–R23
AV
DD
AV
SS
AV
REF
BZ
RESET
TEST
Pin No.
QFP12-48 QFP13-64
7
7
1
1
4
4
13
15
12, 11
14, 13
2
2
3
3
5
5
6
6
40–43
55–58
44–47
59–62
48
63
29–26
36–33
25–22
32–29
21–18
28–25
–
24–21
17–14
20–17
38
53
37
52
35
46
34
45
33–30
44–41
–
40–37
–
10
–
11
10
12
39
54
8
8
9
9
In/Out
–
–
–
–
–
I
O
I
O
I
I
I
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
–
–
–
O
I
I
Function
Power (+) supply pin
Power (–) supply pin
Oscillation/internal logic system regulated voltage output pin
Booster power supply pin
Boosting capacitor connecting pin
Crystal or CR oscillation input pin (selected by mask option)
Crystal or CR oscillation output pin (selected by mask option)
CR or ceramic oscillation input pin (selected by mask option)
CR or ceramic oscillation output pin (selected by mask option)
Input port
Input port
Input port (key-position detect interrupt port)
I/O port
I/O port (switching to serial I/F input/output is possible by software)
I/O port
I/O port
I/O port (can be used as A/D converter inputs)
Output port
Output port
Output port (switching to TOUT output is possible by software)
Output port (switching to FOUT output is possible by software)
Output port
Output port
Power (+) supply pin for A/D converter
Power (–) supply pin for A/D converter
Reference voltage for A/D converter
Buzzer output pin
Initial reset input pin
Testing input pin
∗
1
∗
1
∗
2
∗
2
∗1:
P30–P33 and R20–R23 are not available in the QFP12-48pin package.
∗2:
In the QFP12-48pin package, AV
DD
and AV
SS
are connected with V
DD
and V
SS
inside of the IC, respectively.
3
SEIKO [ SEIKO EPSON CORPORATION ]
