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E0C5250 参数 Datasheet PDF下载

E0C5250图片预览
型号: E0C5250
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom IC]
分类和应用:
文件页数/大小: 13 页 / 107 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C5250
Pin name Pin No.
Power-down
Description
state
Active
#RESET
9
Input
Reset input
All of the internal registers are reset to the default state when the pin is set to Low level.
Before any data can be written to the internal registers, this pin must be set to High level.
Active
IMODE
11
Input
Mode selection input: Selects CAS mode or FSK/CPM mode
CAS mode is selected by setting this input to High level, so that CAS detection is enabled
while FSK function/CPM detection is disabled. Also, in this state, data can be written from
the host device to the internal registers using the SDI and #SCLK pins. Note that before
writing data to the internal registers, the serial interface must be synchronized to the data
write sequence by temporarily setting this pin to Low level.
FSK/CPM mode is selected by setting this input to Low level, in which case CAS detection
is disabled and FSK function/CPM detection is enabled. In this state, the host device can
read out receive data from the SDO pin.
V
SS
12 Power supply
Negative power-supply pin
(-)
Connect this pin to the ground line of the system.
Off
13
Input
Crystal oscillator input/external clock input
OSC3
Connect a crystal resonator between this pin and the OSC4 pin and an appropriate
capacitance between this pin and the V
SS
pin. This pin can also be used for external clock
input. In power-down mode, this pin is disconnected from the internal circuit.
High level Crystal oscillator output
14
Output
OSC4
Connect a crystal resonator between this pin and the OSC3 pin and an appropriate
capacitance between this pin and the V
SS
pin. When connecting external clock input to
the OSC3 pin, leave this pin open. During power-down mode, this pin changes to High
level.
High level Prequalify output
Output
#PQUAL 16
The prequalify status of the CAS tone can be monitored from this pin in CAS mode. This
pin returns to High level when the CAS tone is not detected.
Active
17
Output
#DET
Detection output
During power-down mode, this pin changes to Low level when a ring signal is input or
pulled to Low level by the Line Reversal signal. During normal operation in FSK mode,
this pin goes to Low level when an FSK signal is input. During normal operation in CPM
mode, this pin outputs the input signal in pulse form at the amplitude level of V
DD
and
VSS. By measuring the frequency of the pulse from the host side, the CPM (dial) tone can
be identified. During normal operation in CAS mode, this pin goes to Low level when a
CAS tone signal is input.
Active
18
Open-drain
#IRQ
Interrupt request output
output
In power-down mode, this pin changes to Low level when a ring signal is input or pulled to
Low level by the Line Reversal signal. During normal operation in FSK mode, this pin
changes to Low level when receive data is latched into the internal register and is ready to
be read by the host. Then, when the host reads the first bit of the receive data, this pin
returns to High level. During normal operation in CPM mode, this pin changes to Low level
when a signal with a frequency of 200 Hz or above, such as the dial tone, is input. During
normal operation in CAS mode, this pin changes to Low level when the CAS tone is
detected. This pin is held at Low level while the CAS tone is being input.
Active
19
Input
#SCLK
Serial clock input
When the host writes to the internal register or reads receive data, a clock signal is fed
from the host into this pin. The receive data read out by the host is sequentially shifted at
falling edges of the clock signal fed to this pin.
Active
20
Input
SDI
Serial data input
When the host writes to the internal register, the write data is input from this pin.
High level Serial data output
21
Output
SDO
This pin outputs the receive data read out by the host. When asynchronous mode is
selected, data in asynchronous mode is output. When synchronous mode is selected,
data is output synchronously with the clock signal fed to the #SCLK pin by the host. In
power-down, CPM, or CAS mode, this pin is held at High level.
V
REF
22
Input
BPOUT
Capacitor connecting pin
Analog
Connect a 0.1-µF capacitor between this pin and the CDIN pin.
23
Output
CDIN
Capacitor connecting pin
High-Z
Analog
Connect a 0.1-µF capacitor between this pin and the BPOUT pin.
24 Power supply
V
DD
Positive power supply
10,15
Open
Unconnected
N.C.
Type
3