E0C5250
s
BLOCK DIAGRAM
BPOUT
CDIN
Data/timing
recovery
circuit
Detection
circuit
INN
INP
FB
V
REF
#RDET
#RDRC
RDIN
–
Amp
+
Band-pass
filter
CAS tone
filter
FSK
demodulator
Identification
circuit
SDO
#DET
#PQUAL
V
DD
/2
V
DD
Interrupt
control circuit
To other blocks
#IRQ
V
DD
V
SS
Timing
generator
SDI
Control circuit
#SCLK
OSC3 OSC4
PDWN
#RESET
MODE
s
PIN DESCRIPTION
Note: The signal and pin names prefixed by # are those of active-low signals and pins.
Pin name Pin No.
INP
1
Power-down
Description
state
Off
Input
Positive input: Non-inverted amp input
Analog
Connect this pin to the RING side of the twisted-pair telephone line through an input-gain
setting resistor and DC-decoupling capacitor. In power-down mode, this pin is
disconnected from the internal circuit.
Off
Input
Negative input: Inverted amp input
Analog
Connect this pin to the TIP side of the twisted-pair telephone line through an input-gain
setting resistor and DC-decoupling capacitor. In power-down mode, this pin is
disconnected from the internal circuit.
High-Z
Output
Amp output
Analog
Connect a feedback resistor to set the gain between this pin and the INN pin. In power-
down mode, this pin goes to a high-impedance state.
V
DD
level
Output
Reference voltage output
Analog
This pin outputs a voltage that is 1/2 of V
DD
. Connect this pin to V
SS
via a 0.1-µF
capacitor. In power-down mode, this pin outputs a voltage equal to V
DD
.
Schmitt
Active
Ring detection input
trigger input
For ring detection, attenuate the ring signal before inputting it to this pin. This input circuit
remains active even in power-down mode.
Open-drain
Active
Ring detection RC pin
output
Connect an RC network to this pin and set the delay time for ring signal detection. This
Schmitt
output circuit remains active even in power-down mode.
trigger input
Output
Active
Ring detection output
This pin outputs the #RDRC signal after it is passed through a Schmitt trigger buffer.
Upon detection of the ring signal, this pin changes to Low level.
Input
Active
Power-down input
This pin must be held at Low level during normal operation. When the pin is set to High
level, the E0C5250 is placed in power-down mode. During power-down mode, each pin
on the E0C5250 is placed in the state shown in this table.
Type
INN
2
FB
3
V
REF
4
RDIN
5
#RDRC
6
#RDET
7
PDWN
8
2
SEIKO [ SEIKO EPSON CORPORATION ]
