LC78622NE
27. CD-DSP Functional Comparison
Product
LC78626E
(LC78626KE)
LC786021E
LC78625E
LC78630E
LC78624E
LC78622E
LC78622NE
Function
Built-in VCO
FR = 1.2 KΩ
Built-in VCO
FR = 1.2 KΩ
Built-in VCO
FR = 1.2 KΩ
Built-in VCO
FR = 1.2 KΩ
Built-in VCO
FR = 5.1 KΩ
Built-in VCO
FR = 1.2 KΩ
EFM-PLL
RAM
16K
2✕
●
16K
2✕
●
18K
4✕
●
16K
2✕
●
16K
2✕
●
16K
2✕
●
16K
2✕
●
Playback speed
Digital output
Interpolation
4
4
2
2
2
2
2
●
●
●
–∞
●
–∞
●
–∞
●
–∞
●
–∞
Zero-cross muting
–12 dB, –∞
–12 dB, –∞
Level meter peak
search
✕
✕
✕
✕
✕
●
●
Bilingual
●
●
●
●
●
●
●
✕
●
●
●
●
●
●
Digital attenuator
4fs
(8fs)
Digital filters
8fs
8fs
2fs
✕
4fs
8fs
Digital de-emphasis
●
2
●
2
●
2
✕
✕
5
●
●
✕
5
●
(3)
5
Output
I/O
✕
1 + (3)
✕
General-
purpose port
✕
✕
●
(4)
●
●
2 + (4)
●
VCD support
✕
✕
✕
✕
✕
✕
Anti-shock interface
●
Not required
●
Anti-shock control
✕
✕
✕
✕
max 4MDRAM
(max 16MDRAM)
✕
✕
CD text
✕
●
●
✕
✕
●
●
✕
✕
●
●
✕
●
✕
✕
✕
✕
✕
●
●
✕
✕
●
●
✕
✕
●
●
CD-ROM interface
1-bit DAC
L.P.F
3.0 to 5.5 V
(3.0 to 3.6 V)
Supply voltage
Package
3.6 to 5.5 V
QFP80E
3.0 to 5.5 V
QFP80E
3.6 to 5.5 V
QFP80E
3.0 to 5.5 V
QFP64E
3.0 to 5.5 V
QFP64E
3.6 to 5.5 V
QFP64E
QFP100E
Notes on Application Design
While it goes without saying that to achieve system reliability the absolute maximum ratings and allowable operating
conditions specified for this IC must be strictly adhered to, adequate consideration must also be given to the operating
environmental conditions, such as ambient temperature and static electricity, and to the mounting conditions used.
This section presents items that require special care during application design and IC mounting.
Handling of Unused Pins
• If unused input pins on this IC are left in the open state during IC operation, there are times when the IC may enter an
unstable state. Always follow all the directions for handling unused pins included in the documentation for this IC.
Also, do not connect any output pins to power supply, ground, or any other output lines.
• All general-purpose I/O ports must either be set to the output state and set to output a low level in software, or must be
left in the input state and pulled up or pulled down to a fixed input level.
Latch-up Prevention
• Due to the structure of this IC, all supply voltage pins must be supplied with the same potential.
— Also supply the same potential to the servo system ASP. The slice level control circuit is shared with this IC, and
application of the same potential is necessary. Also, the same potential must be supplied to all supply voltage pins
on the ASP IC.
• Latch-up may occur if any discrepancy occurs in the timing of the rise of the supply voltage applied to the different
supply voltage pins. Do not allow timing discrepancies to occur when power is first applied.
• Do not allow the pin voltages on any of the input or output pins to exceed V or to fall lower than V . The timing of
DD
SS
signal application requires special care at power on to assure that this condition is met.
• Do not allow overvoltages or abnormal noise to be applied to this IC.
continued on next page.
No. 6015-28/31
SANYO [ SANYO SEMICON DEVICE ]
