LB1846M, 1848M
Truth Tables
[LB1846M]
IN1
L
IN2
L
IN3
L
IN4
L
OUT1
OFF
H
OUT2
OFF
L
OUT3
OFF
OFF
H
OUT4
OFF
OFF
L
Notes
Standby
H
H
L
L
L
L
L
H
H
H
L
L
H
L
L
L
OFF
L
OFF
H
H
L
L
H
H
H
L
L
H
L
1-2 phase excitation
L
L
L
H
OFF
L
OFF
H
L
L
H
H
H
—
H
L
H
L
L
OFF
H
OFF
L
L
H
H
H
—
L
L
L
H
H
—
—
H
The logic output for the first high-level
input is produced. *2
Note: 1. “—” indicates a “don’t care” input.
2. If two high levels (H/H) are input to the IN1/IN2 pins with the timing shown in ① in the figure below, then the IN2 input that arrived later will be
ignored and the IC will function as though an H/L combination is applied to the IN1/IN2 pins. Similarly, the timing shown in ➁ results in a L/H
combination on the IN1/IN2 pins.
[LB1848M]
ENA
L
IN1
—
L
IN2
—
L
OUT1
OUT2
OUT3
OUT4
Notes
OFF
H
OFF
L
OFF
H
OFF
L
Standby
L
H
H
L
L
H
H
2-phase excitation
H
H
L
H
L
H
H
L
L
H
H
L
Note: “—” indicates a “don’t care” input.
No. 5339-5/8
SANYO [ SANYO SEMICON DEVICE ]
