INSTRUCTION SET
S3C4510B
ASSEMBLER SYNTAX
<LDR|STR>{cond}<H|SH|SB> Rd,<address>
LDR
STR
{cond}
H
Load from memory into a register
Store from a register into memory
Two-character condition mnemonic. See Table 3-2.
Transfer half-word quantity
SB
Load sign extended byte (Only valid for LDR)
Load sign extended half-word (Only valid for LDR)
An expression evaluating to a valid register number.
SH
Rd
<address> can be:
1
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the
expression. This will be a PC relative, pre-indexed address. If the address is out of
range, an error will be generated.
2
A pre-indexed addressing specification:
[Rn]
offset of zero
[Rn,<#expression>]{!}
[Rn,{+/-}Rm]{!}
offset of <expression> bytes
offset of +/- contents of index register
3
A post-indexed addressing specification:
[Rn],<#expression>
[Rn],{+/-}Rm
offset of <expression> bytes
offset of +/- contents of index register.
4
Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the
assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining.
In this case base write-back should not be specified.
{!}
Writes back the base register (set the W bit) if ! is present.
3-38
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