INSTRUCTION SET
CPSR FLAGS
S3C4510B
Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero)
flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is
zero). The C (Carry) flag is set to a meaningless value and the V (overflow) flag is unaffected.
INSTRUCTION CYCLE TIMES
MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle)
and internal (I-cycle), respectively.
m
The number of 8 bit multiplier array cycles is required to complete the multiply,
which is controlled by the value of the multiplier operand specified by Rs.
Its possible values are as follows
1
2
3
4
If bits [32:8] of the multiplier operand are all zero or all one.
If bits [32:16] of the multiplier operand are all zero or all one.
If bits [32:24] of the multiplier operand are all zero or all one.
In all other cases.
ASSEMBLER SYNTAX
MUL{cond}{S} Rd,Rm,Rs
MLA{cond}{S} Rd,Rm,Rs,Rn
{cond}
Two-character condition mnemonic. See Table 3-2.
{S}
Set condition codes if S present
Rd, Rm, Rs and Rn
Expressions evaluating to a register number other than R15.
Examples
MUL
R1,R2,R3
; R1: = R2 * R3
MLAEQS
R1,R2,R3,R4
; Conditionally R1: = R2 * R3 + R4, setting condition
codes.
3-24
SAMSUNG [ SAMSUNG ]
