S3C4510B
INSTRUCTION SET
INSTRUCTION CYCLE TIMES
Data processing instructions vary in the number of incremental cycles taken as follows:
Table 3-4. Incremental Cycle Times
Processing Type
Cycles
Normal data processing
1S
Data processing with register specified shift
Data processing with PC written
1S + 1I
2S + 1N
Data processing with register specified shift and PC written
2S + 1N + 1I
NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively.
ASSEMBLER SYNTAX
— MOV,MVN (single operand instructions).
<opcode>{cond}{S} Rd,<Op2>
— CMP,CMN,TEQ,TST (instructions which do not produce a result).
<opcode>{cond} Rn,<Op2>
— AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC
<opcode>{cond}{S} Rd,Rn,<Op2>
where:
<Op2>
Rm{,<shift>} or,<#expression>
{cond}
A two-character condition mnemonic. See Table 3-2.
Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
Expressions evaluating to a register number.
{S}
Rd, Rn and Rm
<#expression>
If this is used, the assembler will attempt to generate a shifted immediate 8-bit field
to match the expression. If this is impossible, it will give an error.
<shift>
<Shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit
with extend).
<shiftname>s
ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same
code.)
3-17
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