ETHERNET CONTROLLER
S3C4510B
MAC Transmit Control Frame Status
The transmit control frame status register, ETXSTAT, is a RAM-based register which provides the status of a
MAC control packet as it is sent to a remote station. This operation is controlled by the SdPause bit in the
transmit control register, MACTXCON.
It is the responsibility of the DMA engine to read this register, and to generate an interrupt to notify the system
that the transmission of a MAC control packet has been completed.
Table 7-42. ETXSTAT Register
Registers
ETXSTAT
Offset
R/W
Description
Reset Value
0X9040
R
Transmit control frame status
0x00000000
Table 7-43. Transmit Control Frame Register Description
Bit Name Description
Tx_Stat value
Bit Number
[15:0]
A 16-bit value indicating the status of a MAC control packet as
it is sent to a remote station. Read by the DMA engine.
7-46