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S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
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ETHERNET CONTROLLER  
S3C4510B  
MAC FUNCTION BLOCKS  
The major function blocks of the ethernet controller¢s MAC layer are described in Table 7-1 and Figure 7-1.  
Table 7-1. MAC Function Block Descriptions  
Function Block  
Description  
Media Independent  
Interface (MII)  
The interface between the physical layer and the transmit and receive blocks.  
Transmit block  
Moves the outgoing data from the transmit buffer to the MII. The transmit block  
includes circuits for generating the CRC, checking parity, and generating  
preamble or jam. The transmit block also has timers for back-off after collision  
and for the interframe gap the follows a transmission.  
Receive block  
Accepts incoming data from the MII and stores it in the receive FIFO. The  
receive block has logic for computing and checking the CRC value, generating  
parity for data from the MII, and checking minimum and maximum packet  
lengths. The receive block also has a content addressable memory (CAM) block  
which provides for address lookup, and for acceptance or rejection for packets  
based on their destination address.  
Flow control block  
Recognizes MAC control packets and supports the pause operation for full-duplex  
links. The flow control block also supports generation of pause packets, and  
provides timers and counters for pause control.  
MAC control (command)  
and status registers  
Controls programmable options, including the enabling or disabling of signals  
which notify the system when conditions occur. The status registers hold  
information for error handling software, and the error counters accumulate  
statistical information for network management software.  
Loop-back circuit  
Provides for MAC-layer testing in isolation from the MII and physical layer.  
7-4  
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