INSTRUCTION SET
S3C4510B
FORMAT 11: SP-RELATIVE LOAD/STORE
11
10
15
14
13
12
8
7
0
Word 8
1
0
0
1
L
Rd
[7:0] Immediate Value
[10:8] Destination Register
[11] Load/Store Bit
0 = Store to memory
1 = Load from memory
Figure 3-40. Format 11
OPERATION
The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the
following table.
Table 3-18. SP-Relative Load/Store Instructions
L
THUMB Assembler
ARM Equivalent
Action
0
STR Rd, [SP, #Imm]
STR Rd, [R13 #Imm] Add unsigned offset (255 words, 1020 bytes) in Imm to
the current value of the SP (R7). Store the contents of
Rd at the resulting address.
1
LDR Rd, [SP, #Imm]
LDR Rd, [R13 #Imm] Add unsigned offset (255 words, 1020 bytes) in Imm to
the current value of the SP (R7). Load the word from the
resulting address into Rd.
NOTE: The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0),
since the assembler places #Imm >> 2 in the Word8 field.
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-18. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
Examples
STR
R4, [SP,#492]
; Store the contents of R4 at the address
; formed by adding 492 to SP (R13).
; Note that the THUMB opcode will contain
; 123 as the Word8 value.
3-84
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