K9F1208Q0A K9F1216Q0A
K9F1208D0A K9F1216D0A
K9F1208U0A K9F1216U0A
FLASH MEMORY
Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A25
Latches
512M + 16M Bit
NAND Flash
ARRAY
& Decoders
Y-Buffers
Latches
A0 - A7
& Decoders
(512 + 16)Byte x 131072
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC/VCCQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4096 Blocks
= 528 Mbits
128K Pages
(=4,096 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512Byte
16 Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A3
A12
A20
*L
Column Address
Row Address
(Page Address)
A9
A10
A18
*L
A11
A19
*L
A13
A21
*L
A14
A22
*L
A15
A23
*L
A16
A24
*L
A17
A25
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
8
SAMSUNG [ SAMSUNG ]
