K5N1229ACD-BQ12
datasheet
Bank 0
Address
X
Dec
Bank 0
Cell Array
Rev. 1.0
MCP Memory
1.0 FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
Vpp
CLK
CE
OE
WE
WP
RESET
RDY
AVD
I/O
Interface
&
Bank
Control
Bank 1
Address
X
Dec
Latch &
Control
Y Dec
Y Dec
Bank 1
Cell Array
Latch &
Control
Bank 15
Address
X
Dec
Bank 15
Cell Array
Y Dec
A16~A24
A/DQ0~
A/DQ15
Erase
Control
Block
Inform
Program
Control
Latch &
Control
High
Voltage
Gen.
[Table 1] PRODUCT LINE-UP
Mode
Speed Option
Max. Initial Access Time (t
IAA,
ns)
Max. Burst Access Time (t
BA,
ns)
Max. Access Time (t
AA,
ns)
Asynchronous
Max. CE Access Time (t
CE,
ns)
Max. OE Access Time (t
OE,
ns)
1C
(66MHz)
95
11
100
100
15
1D
(83MHz)
95
9
100
100
15
1E
(108MHz)
95
7
100
100
15
1F
(133MHz)
95
6
100
100
15
Synchronous/Burst
V
CC
=1.7V
-1.95V
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