DDR SDRAM 512Mb C-die (x4, x8, x16)
DDR SDRAM
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
8.0 Command Truth Table
A0 ~ A9,
COMMAND
CKEn-1 CKEn CS RAS CAS
WE BA0,1 A10/AP
Note
A11 ~ A12
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
3
3
H
L
L
L
H
X
Entry
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
H
H
H
X
X
X
3
Bank Active & Row Addr.
Read &
Column Address
V
V
Row Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
4
4, 6
7
Column
Address
L
H
L
H
Write &
Column Address
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
H
X
5
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM(UDM/LDM for x16 only)
No operation (NOP) : Not defined
Note :
X
X
8
9
9
H
L
X
H
X
H
1. OP Code : Operand Code. A0 ~ A13& BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges
(Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.1 June. 2005
SAMSUNG [ SAMSUNG ]
