Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
5. DDR3 SDRAM Addressing
1Gb
Configuration
# of Bank
256Mb x 4
8
128Mb x 8
8
64Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
A0 - A13
A0 - A9,A11
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A13
A0 - A9
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A12
A0 - A9
A12/BC
2 KB
Column Address
BC switch on the fly
Page size *1
2Gb
Configuration
# of Bank
512Mb x 4
8
256Mb x 8
8
128Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
A0 - A14
A0 - A9,A11
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A14
A0 - A9
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A13
A0 - A9
A12/BC
2 KB
Column Address
BC switch on the fly
Page size *1
4Gb
Configuration
# of Bank
1Gb x 4
8
512Mb x 8
8
256Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
A0 - A15
A0 - A9,A11
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A15
A0 - A9
A12/BC
1 KB
BA0 - BA2
A10/AP
A0 - A14
A0 - A9
A12/BC
2 KB
Column Address
BC switch on the fly
Page size *1
8Gb
Configuration
# of Bank
2Gb x 4
8
1Gb x 8
8
512Mb x 16
8
Bank Address
Auto precharge
Row Address
BA0 - BA2
A10/AP
BA0 - BA2
A10/AP
A0 - A15
A0 - A9,A11
A12/BC
2 KB
BA0 - BA2
A10/AP
A0 - A15
A0 - A9
A12/BC
2 KB
A0 - A15
A0 - A9,A11,A13
A12/BC
Column Address
BC switch on the fly
Page size *1
2 KB
NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
COLBITS
Page size is per bank, calculated as follows:
page size = 2
* ORG÷8
where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
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SAMSUNG [ SAMSUNG ]
