AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
CLAMP LEVEL DECISION FOR EACH INPUT
*
*
Assume that PGA gain = 1
This flow chart is not fixed, but recommended.
User can modify this algorithm.
Write CIS clamp control register
Set to (111)
[Repeatedly, scan clamp level.
Average ADC output]
Decrease CIS clamp control
register by 1
Scan clamp level input
NO
ADC output > 0
YES
Scan dark line
[MIN(ADC output) = Minimum value of all pixels]
[(100mV)/(4V) * 4096 - 1 = 102]
MIN(ADC output)
> 102
YES
MIN(ADC output)
> 204
YES
NO
NO
NO
MIN(ADC output)
> 0
Increase CIS
clamp control
register by 1
Decrease CIS
clamp control
register by 1
Scan dark line
YES
Increase CIS
clamp control
register by 1
NO
MIN(ADC output)
> 102
YES
Increase CIS
clamp control
register by 1
Go to calibration
20
SAMSUNG [ SAMSUNG ]
