S T S 8215
S amHop Microelectronics C orp.
J an. 10 2008 V er1.0
Dual N-C hannel E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V
DS S
20V
F E AT UR E S
S uper high dense cell design for low R
DS (ON
).
I
D
5A
R
DS (ON) ( m
Ω
) Max
27.5 @ V
G S
= 4.0V
38 @ V
G S
= 2.5V
R ugged and reliable.
S urface Mount P ackage.
E S D P rotected.
D
1
D
2
S OT26
Top View
S1
D1/D2
S2
1
2
3
6
5
4
G1
D1/D2
G2
G
1
G
2
S
1
S
2
ABS OLUTE MAXIMUM R ATINGS (T
A
=25 C unless otherwise noted)
P arameter
Drain-S ource Voltage
Gate-S ource Voltage
Drain C urrent-C ontinuous
a
@ T
J
=25 C
b
-P ulsed
Drain-S ource Diode Forward C urrent
a
Maximum P ower Dissipation
a
Operating Junction and S torage
Temperature R ange
S ymbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
S TG
Limit
20
10
5
24
1.25
1.25
-55 to 150
Unit
V
V
A
A
A
W
C
THE R MAL C HAR AC TE R IS TIC S
Thermal R esistance, Junction-to-Ambient
a
1
R
JA
100
C /W
SAMHOP [ SAMHOP MICROELECTRONICS CORP. ]
