S T G 8203
S amHop Microelectronics C orp.
J un.06 2005 ver1.2
Dual N-C hannel E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V
DS S
20V
F E AT UR E S
( m
Ω
) Max
I
D
5A
R
DS (ON)
S uper high dense cell design for low R
DS (ON
).
27 @ V
G S
= 4.0V
42 @ V
G S
= 2.5V
R ugged and reliable.
S urface Mount P ackage.
( 1 )
D1
D2
( 8 )
T S S OP
1
2
3
4
8
7
6
5
(T OP V IE W)
( 4 )
G1
( 2,3 )
S 1
G2
( 5 )
S 2
( 6,7 )
ABS OLUTE MAXIMUM R ATINGS (T
A
=25 C unless otherwise noted)
P arameter
Drain-S ource Voltage
Gate-S ource Voltage
Drain C urrent-C ontinuous
a
@ T
C
=25 C
b
-P ulsed
Drain-S ource Diode Forward C urrent
a
Maximum P ower Dissipation
a
Operating Junction and S torage
Temperature R ange
S ymbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
S TG
Limit
20
10
5
25
2
1.5
-55 to 150
Unit
V
V
A
A
A
W
C
THE R MAL C HAR AC TE R IS TIC S
Thermal R esistance, Junction-to-Ambient
a
R
JA
85
C /W
1