LM358DT/PT/ST/WDT/WPT,LM2904DT/PT/ST/WDT/WPT
LM324DT/PT/WDT,LM2902DT/PT/WDT
Technical Note
●Circuit Diagram
+
Vcc
INVERTING
INPUT
OUTPUT
NON-INVERTING
INPUT
-
Vcc
Fig.97 Circuit Diagram (each Op-Amp)
●Measurement Circuit 1 NULL Method Measurement Condition
Vcc+, Vcc-, EK, Vicm Unit: [V]
LM2904/LM2902 family
LM358/LM324 family
Parameter
VF S1 S2 S3
Calculation
Vcc+ Vcc- EK Vicm Vcc+ Vcc- EK Vicm
Input Offset Voltage
Input Offset Current
VF1 ON ON OFF 5 to 30
0
0
0
0
0
0
0
0
0
0
-1.4
-1.4
-1.4
-1.4
-1.4
-11.4
-1.4
-1.4
-1.4
-1.4
0
0
5 to 30
0
0
0
0
0
0
0
0
0
0
-1.4
-1.4
-1.4
-1.4
-1.4
-11.4
-1.4
-1.4
-1.4
-1.4
0
0
1
2
VF2 OFF OFF OFF
5
5
5
5
VF3 OFF ON
OFF
0
0
Input Bias Current
3
4
5
6
VF4 ON OFF
5
0
5
0
VF5
15
15
5
0
15
15
5
0
Large Signal Voltage Gain
Common-mode Rejection Ratio
Supply Voltage Rejection Ratio
ON ON ON
VF6
0
0
VF7
0
0
ON ON OFF
VF8
5
3.5
0
5
3.5
0
VF9
5
5
ON ON OFF
VF10
30
0
30
0
－Calculation－
1. Input Offset Voltage (VIO)
0.1[μF]
VF1
1+ Rf /Rs
Vio
[V]
Rf
50[kΩ]
2. Input Offset Current (IIO)
0.1[μF]
500[kΩ]
VF2 - VF1
Iio
[A]
Ri(1+ Rf / Rs)
EK
VOUT
S1
Ri
Vcc+
+15[V]
3. Input Bias Current (IIB)
Rs
VF4 -
VF3
500[kΩ]
[A]
Ib
50[Ω] 10[kΩ]
50[Ω] 10[kΩ]
Vicm
2× Ri (1+ Rf / Rs)
DUT
4. Large Signal Voltage Gain (AVD)
S3
Rs
Ri
S2
Rf 50[kΩ]
1000[pF]
10× (1+ Rf /Rs)
VF6 - VF5
[dB]
AV 20× Log
Vcc-
VF
V
RL
-15[V]
5.Common-mode Rejection Ration (CMRR)
3.5× (1+ Rf/ Rs)
VF8-VF7
[dB]
Log
CMRR 20×
6. Supply Voltage Rejection Ration (SVR)
Vcc+×(1+Rf/Rs)
VF10 - VF9
Fig.98 Measurement circuit1 (Each Op-Amps)
△
[dB]
PSRR 20×Log
＝
Vcc+=25V
△
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2011.06 - Rev.B
12/17
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