APEX 20K Programmable Logic Device Family Data Sheet
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
MultiCore system integration
SignalTap logic analysis
32/64-Bit, 33-MHz PCI
32/64-Bit, 66-MHz PCI
MultiVolt I/O
APEX 20K Devices
Full support
Full support
Full compliance in -1, -2 speed
grades
-
2.5-V or 3.3-V V
CCIO
V
CCIO
selected for device
Certain devices are 5.0-V tolerant
Clock delay reduction
2× and 4× clock multiplication
APEX 20KE Devices
Full support
Full support
Full compliance in -1, -2 speed grades
Full compliance in -1 speed grade
1.8-V, 2.5-V, or 3.3-V V
CCIO
V
CCIO
selected block-by-block
5.0-V tolerant with use of external resistor
Clock delay reduction
m
/(n
×
v)
or
m
/(n
×
k)
clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Eight
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
GTL+
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
(in EP20K300E and larger devices)
LVDS and LVPECL clock pins (in all BGA
and FineLine BGA devices)
LVDS and LVPECL data pins up to
156 Mbps (in -1 speed grade devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
CAM
Dual-port RAM
FIFO
RAM
ROM
ClockLock support
Dedicated clock and input pins Six
I/O standard support
2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
Low-voltage transistor-to-transistor
logic (LVTTL)
Memory support
Dual-port RAM
FIFO
RAM
ROM
Altera Corporation
7
ROCHESTER [ Rochester Electronics ]
