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EP20K200RC208-1X 参数 Datasheet PDF下载

EP20K200RC208-1X图片预览
型号: EP20K200RC208-1X
PDF下载: 下载PDF文件 查看货源
内容描述: [LOADABLE PLD, 2.5 ns, PQFP208, RQFP-208]
分类和应用: 可编程逻辑
文件页数/大小: 127 页 / 2397 K
品牌: ROCHESTER [ Rochester Electronics ]
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APEX 20K Programmable Logic Device Family Data Sheet  
APEX 20K devices incorporate LUT-based logic, product-term-based  
logic, and memory into one device. Signal interconnections within  
APEX 20K devices (as well as to and from device pins) are provided by the  
FastTrack Interconnect—a series of fast, continuous row and column  
channels that run the entire length and width of the device.  
Functional  
Description  
Each I/ O pin is fed by an I/ O element (IOE) located at the end of each row  
and column of the FastTrack Interconnect. Each IOE contains a  
bidirectional I/ O buffer and a register that can be used as either an input  
or output register to feed input, output, or bidirectional signals. When  
used with a dedicated clock pin, these registers provide exceptional  
performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,  
66-MHz PCI compliance; JTAG BST support; slew-rate control; and  
tri-state buffers. APEX 20KE devices offer enhanced I/ O support,  
including support for 1.8-V I/ O, 2.5-V I/ O, LVCMOS, LVTTL, LVPECL,  
3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V  
AGP I/ O standards.  
The ESB can implement a variety of memory functions, including CAM,  
RAM, dual-port RAM, ROM, and FIFO functions. Embedding the  
memory directly into the die improves performance and reduces die area  
compared to distributed-RAM implementations. Moreover, the  
abundance of cascadable ESBs ensures that the APEX 20K device can  
implement multiple wide memory blocks for high-density designs. The  
ESB’s high speed ensures it can implement small memory blocks without  
any speed penalty. The abundance of ESBs ensures that designers can  
create as many different-sized memory blocks as the system requires.  
Figure 1 shows an overview of the APEX 20K device.  
Figure 1. APEX 20K Device Block Diagram  
Clock Management Circuitry  
FastTrack  
Interconnect  
IOE  
IOE  
ClockLock  
IOE  
LUT  
IOE  
LUT  
LUT  
IOE  
Four-input LUT  
for data path and  
DSP functions.  
LUT  
LUT  
IOE  
Product Term  
Memory  
Product Term  
Memory  
Product Term  
Memory  
Product Term  
Memory  
IOEs support  
PCI, GTL+,  
SSTL-3, LVDS,  
and other  
Product-term  
integration for  
high-speed  
control logic and  
state machines.  
standards.  
LUT  
LUT  
LUT  
Product Term  
Memory  
LUT  
Product Term  
Memory  
Product Term  
Memory  
IOE  
IOE  
Product Term  
Memory  
Flexible integration  
of embedded  
memory, including  
CAM, RAM,  
IOE  
IOE  
IOE  
IOE  
ROM, FIFO, and  
other memory  
functions.  
Altera Corporation  
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