ADV7127
CIRCUIT DESCRIPTION AND OPERATION
The ADV7127 contains one 10-bit D/A converter, with one
input channel containing a 10-bit register. A reference amplifier
is also integrated on board the part.
All video data and control inputs are latched into the ADV7127
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7127 be driven by a TTL buffer (e.g., 74F244).
Digital Inputs
I
OUT
Ten bits of data (color information) D0–D9 are latched into the
device on the rising edge of each clock cycle. This data is pre-
sented to the 10-bit DAC and is then converted to an analog
output waveform. See Figure 20.
mA
V
WHITE
LEVEL
17.61
0.66
CLOCK
100 IRE
DIGITAL INPUTS
DATA
BLACK
LEVEL
D0–D9
0
0
Figure 21. IOUT Video Output Waveform
ANALOG OUTPUTS
I
, I
OUT
OUT
Table I. Video Output Truth Table (RSET = 560 ⍀,
LOAD = 37.5 ⍀)
R
Figure 20. Video Data Input/Output
Description
Data
DAC
Input
All these digital inputs are specified to accept TTL logic levels.
IOUT
IOUT
Clock Input
The CLOCK input of the ADV7127 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following equation:
WHITE LEVEL
VIDEO
BLACK LEVEL
17.62
Video
0
0
3FF
17.62 – Video Data
17.62 000H
Power Management
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
The PSAVE input of the ADV7127 puts the part into standby
mode. It is used to reduce power consumption. When PSAVE
is low, the power may be reduced to approximately 10 mW at
3 V. The ADV7127 in TSSOP package also has a power-down
feature where the entire part, including the voltage reference
circuit, is powered down. In this case, power on the ADV7127
can be reduced to 60 µW at 3 V.
Horiz Res
Vert Res
= Number of Pixels/Line.
= Number of Lines/Frame.
Refresh Rate
= Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typically
60 Hz for a noninterlaced system or 30 Hz
for an interlaced system.
Table II. Power Management
Retrace Factor = Total Blank Time Factor. This takes into
account that the display is blanked for a
certain fraction of the total duration of each
frame (e.g., 0.8).
Mode
ADV7127 TSSOP
ADV7127 SOIC
Power-Save 10 mW Typically at 3 V 10 mW Typically at 3 V
Power-Down Power 60 µW at 3 V
Not Available
Therefore, if we have a graphics system with
a 1024 × 1024 resolution, a noninterlaced
60 Hz refresh rate and a retrace factor of 0.8,
then:
Reference Input
The ADV7127 has an on-board voltage reference. The VREF
pin is normally terminated to VAA through a 0.1 µF capacitor.
Alternatively, the part could, if required, be overdriven by an
external 1.23 V reference (AD1580).
Dot Rate
= 1024 × 1024 × 60/0.8
= 78.6 MHz
A resistance RSET connected between the RSET pin and GND
determines the amplitude of the output video level according to
the following equation:
The required CLOCK frequency is thus 78.6 MHz.
IOUT (mA) = 7,968 × VREF(V)/RSET(Ω)
(1)
Using a variable value of RSET, as shown in Figure 22, allows
for accurate adjustment of the analog output video levels. Use
of a fixed 560 Ω RSET resistor yields the analog output levels
as quoted in the specification page. These values typically
correspond to the RS-343A video waveform values as shown in
Figure 21.
–12–
REV. 0
ROCHESTER [ Rochester Electronics ]
