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ADSP-BF532SBBZ400 参数 Datasheet PDF下载

ADSP-BF532SBBZ400图片预览
型号: ADSP-BF532SBBZ400
PDF下载: 下载PDF文件 查看货源
内容描述: [16-BIT, 40 MHz, OTHER DSP, PBGA169, ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169]
分类和应用: 时钟外围集成电路
文件页数/大小: 65 页 / 5323 K
品牌: ROCHESTER [ Rochester Electronics ]
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ADSP-BF531/ADSP-BF532/ADSP-BF533  
GENERAL DESCRIPTION  
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are  
members of the Blackfin® family of products, incorporating the  
Analog Devices, Inc./Intel Micro Signal Architecture (MSA).  
Blackfin processors combine a dual-MAC state-of-the-art signal  
processing engine, the advantages of a clean, orthogonal RISC-  
like microprocessor instruction set, and single instruction, mul-  
tiple data (SIMD) multimedia capabilities into a single  
instruction set architecture.  
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are  
completely code and pin-compatible, differing only with respect  
to their performance and on-chip memory. Specific perfor-  
mance and memory configurations are shown in Table 1.  
PORTABLE LOW POWER ARCHITECTURE  
Blackfin processors provide world-class power management  
and performance. Blackfin processors are designed in a low  
power and low voltage design methodology and feature  
dynamic power management—the ability to vary both the volt-  
age and frequency of operation to significantly lower overall  
power consumption. Varying the voltage and frequency can  
result in a substantial reduction in power consumption, com-  
pared with just varying the frequency of operation. This  
translates into longer battery life for portable appliances.  
SYSTEM INTEGRATION  
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are  
highly integrated system-on-a-chip solutions for the next gener-  
ation of digital communication and consumer multimedia  
applications. By combining industry-standard interfaces with a  
high performance signal processing core, users can develop  
cost-effective solutions quickly without the need for costly  
external components. The system peripherals include a UART  
port, an SPI port, two serial ports (SPORTs), four general-pur-  
pose timers (three with PWM capability), a real-time clock, a  
watchdog timer, and a parallel peripheral interface.  
Table 1. Processor Comparison  
Features  
SPORTs  
2
2
2
UART  
1
1
1
SPI  
1
1
1
PROCESSOR PERIPHERALS  
GP Timers  
3
3
3
Watchdog Timers  
1
1
1
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con-  
tain a rich set of peripherals connected to the core via several  
high bandwidth buses, providing flexibility in system configura-  
tion as well as excellent overall system performance (see the  
functional block diagram in Figure 1 on Page 1). The general-  
purpose peripherals include functions such as UART, timers  
with PWM (pulse-width modulation) and pulse measurement  
capability, general-purpose I/O pins, a real-time clock, and a  
watchdog timer. This set of functions satisfies a wide variety of  
typical system support needs and is augmented by the system  
expansion capabilities of the part. In addition to these general-  
purpose peripherals, the processors contain high speed serial  
and parallel ports for interfacing to a variety of audio, video, and  
modem codec functions; an interrupt controller for flexible  
management of interrupts from the on-chip peripherals or  
external sources; and power management control functions to  
tailor the performance and power characteristics of the proces-  
sor and system to many application scenarios.  
RTC  
1
1
1
Parallel Peripheral Interface  
GPIOs  
1
1
1
16  
16  
16  
L1 Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes  
L1 Instruction SRAM  
L1 Data SRAM/Cache  
L1 Data SRAM  
16K bytes 32K bytes 64K bytes  
16K bytes 32K bytes 32K bytes  
32K bytes  
L1 Scratchpad  
4K bytes 4K bytes 4K bytes  
1K bytes 1K bytes 1K bytes  
L3 Boot ROM  
Maximum Speed Grade  
400 MHz 400 MHz 600 MHz  
Package Options:  
CSP_BGA  
Plastic BGA  
LQFP  
160-Ball 160-Ball 160-Ball  
169-Ball 169-Ball 169-Ball  
176-Lead 176-Lead 176-Lead  
All of the peripherals, except for general-purpose I/O, real-time  
clock, and timers, are supported by a flexible DMA structure.  
There is also a separate memory DMA channel dedicated to  
data transfers between the processor’s various memory spaces,  
including external SDRAM and asynchronous memory. Multi-  
ple on-chip buses running at up to 133 MHz provide enough  
bandwidth to keep the processor core running along with activ-  
ity on all of the on-chip and external peripherals.  
By integrating a rich set of industry-leading system peripherals  
and memory, Blackfin processors are the platform of choice for  
next generation applications that require RISC-like program-  
mability, multimedia support, and leading-edge signal  
processing in one integrated package.  
The processors include an on-chip voltage regulator in support  
of the processor’s dynamic power management capability. The  
voltage regulator provides a range of core voltage levels from  
V
DDEXT. The voltage regulator can be bypassed at the user’s  
discretion.  
Rev. H  
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Page 3 of 64  
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January 2011  
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