欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADM3491AR-REEL 参数 Datasheet PDF下载

ADM3491AR-REEL图片预览
型号: ADM3491AR-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: [LINE TRANSCEIVER, PDSO14, MS-012AB, SOIC-14]
分类和应用: 驱动信息通信管理光电二极管接口集成电路驱动器
文件页数/大小: 21 页 / 1325 K
品牌: ROCHESTER [ Rochester Electronics ]
 浏览型号ADM3491AR-REEL的Datasheet PDF文件第5页浏览型号ADM3491AR-REEL的Datasheet PDF文件第6页浏览型号ADM3491AR-REEL的Datasheet PDF文件第7页浏览型号ADM3491AR-REEL的Datasheet PDF文件第8页浏览型号ADM3491AR-REEL的Datasheet PDF文件第10页浏览型号ADM3491AR-REEL的Datasheet PDF文件第11页浏览型号ADM3491AR-REEL的Datasheet PDF文件第12页浏览型号ADM3491AR-REEL的Datasheet PDF文件第13页  
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
Data Sheet  
RO  
RE  
DE  
DI  
1
2
3
4
8
7
6
5
V
CC  
ADM3483/  
ADM3485  
TOP VIEW  
(Not to Scale)  
B
A
GND  
Figure 4. ADM3483/ADM3485 Pin Configuration  
V
1
2
3
4
8
7
6
5
A
B
Z
CC  
ADM3488/  
ADM3490  
TOP VIEW  
(Not to Scale)  
RO  
DI  
GND  
Y
Figure 5. ADM3488/ADM3490 Pin Configuration  
NC  
RO  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
V
CC  
CC  
RE  
A
ADM3491  
DE  
TOP VIEW  
B
(Not to Scale)  
DI  
Z
GND  
GND  
Y
8
NC  
NC = NO CONNECT  
Figure 6. ADM3491 Pin Configuration  
Table 7. Pin Function Descriptions  
ADM3483/ ADM3488/  
ADM3485 Pin No. ADM3490 Pin No. Pin No.  
ADM3491  
Mnemonic Description  
1
2
2
RO  
Receiver Output. When enabled, if A > B by 200 mV, then RO =  
high. If A < B by 200 mV, then RO = low.  
2
Not applicable  
3
RE  
Receiver Output Enable. A low level enables the receiver output,  
RO. A high level places it in a high impedance state. If RE is high  
and DE is low, the device enters a low power shutdown mode.  
3
4
Not applicable  
4
5
DE  
DI  
Driver Output Enable. A high level enables the driver differential  
Output A and Output B. A low level places it in a high impedance  
state. If RE is high and DE is low, the device enters a low power  
shutdown mode.  
Driver Input. With a half-duplex part when the driver is enabled, a  
logic low on DI forces A low and B high while a logic high on DI  
forces A high and B low. With a full-duplex part when the driver is  
enabled, a logic low on DI forces Y low and Z high while a logic  
high on DI forces Y high and Z low.  
3
5
4
5
6
6, 7  
9
10  
GND  
Y
Z
Ground.  
Noninverting Driver Output.  
Inverting Driver Output.  
Not applicable  
Not applicable  
6
Not applicable  
8
Not applicable  
7
Not applicable  
12  
Not applicable  
11  
13, 14  
1, 8  
A
A
B
B
VCC  
NC  
Noninverting Receiver Input A and Noninverting Driver Output A.  
Noninverting Receiver Input A.  
Inverting Receiver Input B and Inverted Driver Output B.  
Inverting Receiver Input B.  
Power Supply (3.3 V 0.3 V).  
No Connect.  
Not applicable  
7
Not applicable  
8
Not applicable  
1
Not applicable  
Rev. E | Page 8 of 20  
 
 复制成功!