AD9888
TIMING
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
Register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
The following timing diagrams show the operation of the AD9888
analog interface in all clock modes. The part establishes timing
by sending the sample that corresponds to the pixel digitized
when the leading edge of Hsync occurs sent to the “A” data port.
In dual-channel mode, the next sample is to the “B” port. Future
samples are alternated between the “A” and “B” data ports. In
single-channel mode, data is only sent to the “A” data port, and
the “B” port is placed in a high impedance state.
Three things happen to Horizontal Sync in the AD9888. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via
Register 07H. HSOUT is the sync signal that should be used to
drive the rest of the display system.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
tPER
tDCYCLE
COAST Timing
In most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
DATACK
DATACK
In some systems, however, Hsync is disturbed during the Verti-
cal Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-On-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync.
To avoid upsetting the clock generator during Vsync, it is impor-
tant to ignore these distortions. If the pixel clock PLL sees
extraneous pulses, it will attempt to lock to this new frequency,
and will have changed frequency by the end of the Vsync period.
It will then take a few lines of correct Hsync timing to recover at
the beginning of a new frame, resulting in a “tearing” of the
image at the top of the display.
tSKEW
DATA
HSOUT
Figure 12. Output Timing
Hsync Timing
Horizontal sync is processed in the AD9888 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
REV. B
–13–
ROCHESTER [ Rochester Electronics ]
