AD9884A
CLOCK GENERATOR CONTROL
0D
3–1
REVID
Silicon Revision ID
0B
7–3
PHASE
Clock Phase Adjust
The die revision of the AD9884A can be determined by reading
these three bits.
A five-bit value that adjusts the sampling phase in 32 steps across
one pixel time. Each step represents an 11.25 degree shift in
sampling phase.
Serial Control Port
A 2-wire serial control interface is provided. Up to four AD9884A
devices may be connected to the 2-wire serial interface, with
each device having a unique address.
The power-up default value is PHASE = 16.
0C
6–5
VCORNGE
VCO Range Select
The 2-wire interface comprises a clock (SCL) and a bidirec-
tional data (SDA) pin. The Analog Flat Panel Interface acts as a
slave for receiving and transmitting data over the serial interface.
When the serial interface is not active, the logic levels on SCL
and SDA are pulled HIGH by external pull-up resistors.
Two bits that establish the operating range of the clock generator.
VCORNGE
Range (MHz)
00
01
10
11
20-60
50-90
80-120
110-140
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA
must change only when SCL is LOW. If SDA changes state
while SCL is HIGH, the serial interface interprets that action as
a start or stop sequence.
VCORNGE must be set to correspond with the desired operat-
ing frequency (incoming pixel rate).
There are six components to serial bus operation:
• Start Signal
• Slave Address Byte
• Base Register Address Byte
• Data Byte to Read or Write
• Stop Signal
The power-up default value is VCORNGE = 01.
0C
4–2
CURRENT
Charge Pump Current
Three bits that establish the current driving the loop filter in the
clock generator.
When the serial interface is inactive (SCL and SDA are HIGH)
communications are initiated by sending a start signal. The start
signal is a HIGH-to-LOW transition on SDA while SCL is
HIGH. This signal alerts all slaved devices that a data transfer
sequence is coming.
CURRENT
Current (A)
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
The first eight bits of data transferred after a start signal com-
prising a seven bit slave address (the first seven bits) and a
single R/W bit (the eighth bit). The R/W bit indicates the direc-
tion of data transfer, read from (1) or write to (0) the slave
device. If the transmitted slave address matches the address of
the device (set by the state of the SA1-0 input pins in Table IV),
the AD9884A acknowledges by bringing SDA LOW on the
ninth SCL pulse. If the addresses do not match, the AD9884A
does not acknowledge.
CURRENT must be set to correspond with the desired operat-
ing frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
Table IV. Serial Port Addresses
0D
4
OUTPHASE
Output Port Phase
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
One bit that determines whether even pixels or odd pixels go to
Port A.
A6
A5
A4
A3
A2
A1
A0
R/W
(MSB)
(LSB)
OUTPHASE
First Pixel After HSYNC
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Port A
Port B
In normal operation (OUTPHASE = 0), when operating in
Dual Channel output mode (DEMUX = 1), the first sample
after the HSYNC leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN samples
go to Port B.
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9884A does not acknowledge the master device during
a write sequence, the SDA remains HIGH so the master can
generate a stop signal. If the master device does not acknowl-
edge the AD9884A during a read sequence, the AD9884A inter-
prets this as “end of data.” The SDA remains HIGH so the
master can generate a stop signal.
When OUTPHASE = 1, these ports are reversed and the first
sample goes to Port B.
When DEMUX = 0, this bit is ignored.
When reading back the value of OUTPHASE, the bit appears at
register 0D, Bit 7.
–12–
REV. C
ROCHESTER [ Rochester Electronics ]
