AD9884A
Table III. Default Register Values
CONTROL REGISTER MAP
The AD9884A is initialized and controlled by a set of registers
that determine the operating modes. An external controller is
employed to write and read the control registers through the
2-line serial interface port.
Reg
Value
Reg
Value
00
01
02
03
04
05
06
07
01101001
1101 0000
10000000
10000000
10000000
100000 00
100000 00
100000 00
69h
D0h
80h
80h
80h
80h
80h
80h
08
09
10000000
10000000
11110100
10000 000
80h
80h
F4h
80h
0A
0B
0C
0D
0E
0F
Table II. Control Register Map
0 01 001 00 24h
Reg Bit Default
Mnemonic Function
00000000
0000xxx0
00000000
00h
0xh
00h
PLL Divider Control
00 7–0 01101001 PLLDIVM PLL Divide Ratio MSBs
01 7–4 1101
PLLDIVL
PLL Divide Ratio LSBs
Reserved, Set to Zero
••••
01 3–0
0000
••••
CONTROL REGISTER DETAIL
PLL DIVIDER CONTROL
Input Gain
02 7–0 10000000 REDGAIN Red Channel Gain Adjust
03 7–0 10000000 GRNGAIN Green Channel Gain Adjust
04 7–0 10000000 BLUGAIN Blue Channel Gain Adjust
00
7–0
PLLDIVM
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
Input Offset
05 7–2 100000
REDOFST Red Channel Offset Adjust
••
00 Reserved, Set to Zero
The PLL derives a master clock from an incoming HSYNC signal.
The master clock frequency is then divided by an integer value,
and the divider’s output is phase-locked to HSYNC. This PLLDIV
value determines the number of pixel times (pixels plus horizontal
blanking overhead) per line. This is typically 20% to 30% more
than the number of active pixels in the display.
05 1–0
06 7–2 100000
••••••
GRNOFST Green Channel Offset Adjust
••
00 Reserved, Set to Zero
06 1–0
••••••
07 7–2 100000
BLUOFST Blue Channel Offset Adjust
••
00 Reserved, Set to Zero
07 1–0
••••••
The 12-bit value of PLLDIV supports divide ratios from 2 to 4095.
The higher the value loaded in this register, the higher the resulting
clock frequency with respect to a fixed HSYNC frequency.
Clamp Timing
08 7–0 10000000 CLPLACE Clamp Placement
09 7–0 10000000 CLDUR
Clamp Duration
VESA has established some standard timing specifications, which
will assist in determining the value for PLLDIV as a function of
horizontal and vertical display resolution and frame rate (Table
VII). However, many computer systems do not conform precisely
to the recommendations, and these numbers should be used only
as a guide. The display system manufacturer should provide auto-
matic or manual means for optimizing PLLDIV. An incorrectly set
PLLDIV will usually produce one or more vertical noise bars on
the display. The greater the error, the greater the number of bars
produced.
General Control 1
0A
0A
0A
0A
0A
0A
0A
0A
7
6
5
4
3
2
1
0
1
DEMUX
PAR
HSPOL
CSTPOL
EXTCLMP Clamp Signal Source
CLAMPOL Clamp Signal Polarity
EXTCLK
Output Port Select
Output Timing Select
HSYNC Polarity
COAST Polarity
•••••••
1
• ••••••
••
1
•••••
1
••• ••••
0
1
•••• •••
••••• ••
0
External Clock Select
Reserved, Set to Zero
•••••• •
0
•••••••
Clock Generator Control
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69h, PLLDIVL = Dxh).
0B 7–3 10000
PHASE
Clock Phase Adjust
Reserved, Set to Zero
Reserved, Set to Zero
•••
0B 2–0
000
•••••
0C
7
0
•••••••
01
7–4
PLLDIVL
PLL Divide Ratio LSBs
0C 6–5 01
0C 4–2
0C 1–0
VCORNGE VCO Range Select
CURRENT Charge Pump Current
Reserved, Set to Zero
• •••••
001
••• ••
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
00
••••••
General Control 2
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69h, PLLDIVL = Dxh).
0D 7–5 000
Reserved, Set to Zero
•••••
000 REVID
0D
0D 3–1
0D
4
0
OUTPHASE Output Port Phase
••• ••••
Die Revision ID
Reserved, Set to Zero
Reserved, Set to Zero
•••• •
0
0
•••••••
0E 7–0 00000000
REV. C
–9–
ROCHESTER [ Rochester Electronics ]
