Operation of Output Delay
ꢀ
Released Voltage (+VDET
)
Supply Voltage
Capacitor Voltage
Output Voltage
CD Pin Threshold Voltage (VTCD
GND
)
GND
Output Delay Time ( )
D
t
When the Supply Voltage which is higher than Released Voltage is forced to VDD pin, charge to an
external capacitor starts, then capacitor voltage increases. Until the capacitor voltage reaches to CD
Pin Threshold Voltage, Output Voltage maintains “L”. When the capacitor voltage becomes higher than
CD pin threshold voltage, Output Voltage is reversed from “L” to “H”. Where, the time interval between
the rising edge of Supply Voltage and Output Voltage Reverse point means Output Delay Time.
Output Delay Time
ꢀ
Output Delay Time (tD) can be calculated with the next formula.
D(s)
D
D
t =0.69ꢀR ꢀC
RD is internal resistor and set at 6.5M (TYP.) typically. CD(F) describes the capacitance value of an
Ω
external capacitor. Therefore,
6
D
D(s)
t =0.69ꢀ6.5ꢀ10 ꢀC
Rev. 1.10
- 3 -
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
