RT8206A/B
Functional Pin Description
REF (Pin 1)
VOUT1 (Pin 10)
2V Reference Output. Bypass to GND with a 0.22uF
capacitor. REF can source up to 50uA for external loads.
Loading REF degrades FBx and output accuracy according
to the REF load-regulation error.
SMPS1 Output Voltage-Sense Input. Connect this pin to
the SMPS1 output. VOUT1 is an input to the Constant
on-time-PWM one-shot circuit. It also serves as the
SMPS1 feedback input in fixed-voltage mode.
TON (Pin 2)
FB1 (Pin 11)
Frequency Select Input. (VOUT1/VOUT2 switching
frequency, respectively) :
SMPS1 Feedback Input. Connect FB1 to VCC orGNDfor
fixed 5V operation. Connect FB1 to a resistive voltage-
divider from VOUT1 to GND to adjust output from 2V to
5.5V.
TON = VCC, (200kHz / 250kHz)
TON = REF, (300kHz / 375kHz)
TON = GND, (400kHz / 500kHz)
ILIM1 (Pin 12)
SMPS1 Current-Limit Adjustment. The GND − PHASE1
current-limit threshold is 1/10th the voltage seen at ILIM1
over a 0.5V to 2V range. There is an internal 5uA current
source from VCC to ILIM1. The logic current limit threshold
is default to 100mV if ILIM1 is higher than (VCC − 1V).
VCC (Pin 3)
Analog Supply Voltage Input for the PWM Core. Bypass
to GND with a 1uF ceramic capacitor
ENLDO (Pin 4)
LDO Enable Input. The REF/LDO is enabled if ENLDO is
within logic high level and disable if ENLDO is less than
the logic low level.
PGOOD1 (Pin 13)
SMPS1 Power-Good Open-Drain Output. PGOOD1 is low
when the SMPS1 output voltage is more than 7.5% below
the normal regulation point or during soft-start. PGOOD1
is high impedance when the output is in regulation and
the soft-start circuit has terminated. PGOOD1 is low in
shutdown.
NC (Pin 5, 8)
No Internal Connection.
VIN (Pin 6)
Power-supply Input. VIN is used for the constant on-time
PWM one shot circuits. VIN is also used to power the
linear regulators. The linear regulators are powered by
SMPS1 if VOUT1 is set greater than 4.66V and BYP is
tied to VOUT1. Connect VIN to the battery input and
bypass with a 1uF capacitor.
EN1 (Pin 14)
SMPS1 Enable Input. The SMPS1 will be enabled if EN1
is greater than the logic high level and disabled if EN1 is
less than the logic low level. If EN1 is connected to REF,
the SMPS1 starts after the SMPS2 reaches regulation
(delay start).Drive EN1 below 0.8V to clear fault level and
reset the fault latches.
LDO (Pin 7)
Linear-Regulator Output. LDO can provide a total of 70mA
external loads. The LDO regulates a fixed 5V output. When
the BYP is within 5V switchover threshold, the internal
regulator shuts down and the LDO output pin connects to
BYP through a 1.5Ω switch. Bypass LDO output with a
minimum of 4.7uF ceramic.
UGATE1 (Pin 15)
High-Side MOSFET Floating Gate-Driver Output for
SMPS1. UGATE1 swings between PHASE1 and BOOT1.
PHASE1 (Pin 16)
Inductor Connection for SMPS1. PHASE1 is the internal
lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.
BYP (Pin 9)
BYP is the switchover source voltage input for the LDO.
DS8206A/B-03 December 2009
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RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
