RT8004
As an example, consider the RT8004 in dropout at an
input voltage of 3.3V, a load current of 3Aand an ambient
temperature of 70°C. From the typical performance graph
of switch resistance, the RDS(ON) of the P-Channel switch
at 70°C is approximately 97mΩ. Therefore, power
dissipated by the part is :
ꢀ LX node is with high frequency voltage swing and should
be kept small area. Keep all sensitive small-signal nodes
away from LX node to prevent stray capacitive noise
pick-up.
ꢀ Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. You can connect the copper areas
to any DC net (PVIN, SVIN, VOUT, PGND, SGND, or
any other DC rail in your system).
PD = (ILOAD)2 (RDS(ON)) = (3A)2 (97mΩ) = 0.873W
For the TSSOP package, the θJA is 47°C/W. Thus the
junction temperature of the regulator is :
ꢀ Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
andGND.
TJ = 70°C+(0.873W) (47°C/W) = 111°C
Which is below the maximum junction temperature of
125°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD(ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
The COMP pin external components and output capacitor
shown in TypicalApplication Circuit will provide adequate
compensation for most applications.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8004.
ꢀ Aground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
ꢀ Connect the terminal of the input capacitor(s), CIN, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.
DS8004-03 September 2007
www.richtek.com
13
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
