RT7258
For WDFN-14L 4x3 package, the thermal resistance, θJA,
is 60°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formulas :
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7258.
` Keep the traces of the main current paths as short and
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
wide as possible.
SOP-8 (Exposed Pad) package
` Put the input capacitor as close as possible to the device
PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
pins (VINandGND).
WDFN-14L 4x3 package
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick-up.
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT7258 package, the derating
curves in Figure 8 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7258.
1.8
` Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
Four-Layer PCB
1.6
1.4
1.2
` An example of PCB layout guide is shown in Figure 9
WDFN-14L 4x3
1.0
and Figure 10 for reference.
0.8
SOP-8 (Exposed Pad)
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8.Derating Curves for RT7258 Package
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7258-00 January 2012
www.richtek.com
15
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