RT7231/32/33/34
Layout Consideration
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Four-Layer PCB
Follow the PCB layout guidelines for optimal performance
of the RT7231/32/33/34
TSSOP-14 (Exposed Pad)
Keep the traces of the main current paths as short and
SOP-8 (Exposed Pad)
wide as possible.
Put the input capacitor as close as possible to the device
WDFN-10L 3x3
pins (VINandGND).
SW node is with high frequency voltage swing and
should be kept at small area. Keep sensitive
components away from the SW node to prevent stray
capacitive noise pickup.
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum PowerDissipation
Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7231/32/33/34 FB pin.
The GND and Exposed Pad should be connected to a
strong ground plane for heat sinking and noise protection.
Place the feedback components
as close to the FB as possible
for better regulation.
Place the feedback components
Place the input and output
Place the input and output
capacitors as close to the
IC as possible.
as close to the FB as possible
capacitors as close to the
for better regulation.
IC as possible.
PGND
V
OUT
PGND
R1
C
C
IN
IN
R2
14
13
VOUT
FB
PVCC
SS
GND
PGOOD
EN
VINR
VIN
C
1
2
3
10
EN
FB
PVCC
R1
VIN
VIN
BOOT
SW
SW
2
C
V
9
8
7
6
BOOT
OUT
3
12
11
10
9
BOOT
SW
BOOT
L
R2
C
VCC
4
5
6
7
PGND
4
5
SS
C
VCC
11
SW
PGND
PGND
PGOOD
L
V
OUT
15
C
OUT
8
C
OUT
PGND
V
OUT
SW should be connected to inductor by
Wide and short trace. Keep sensitive
components away from this trace.
SW should be connected to inductor by wide and short
trace. Keep sensitive components away from this trace.
(a). For TSSOP-14 (Exposed Pad) Package
(b). For WDFN-10L 3x3 Package
The resistor divider must
be connected as close to
the device as possible.
Input capacitor must be placed
as close to the IC as possible.
C1
C2
V
OUT
SW should be connected to inductor by
Wide and short trace. Keep sensitive
components away from this trace.
R1
8
7
6
5
EN
FB
VIN
R2
C4
C5
2
3
4
BOOT
SW
GND
C6
GND
PVCC
SS
9
L1
GND
C7
(c). For SOP-8 (Exposed) Package
Figure 7. PCB Layout Guide
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7231/32/33/34-09 October 2016
www.richtek.com
15
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
