RT7231/32/33/34
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, VIN. A sudden inrush of current through the long
wires can potentially cause a voltage spike at VIN large
enough to damage the part.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
External Bootstrap Diode
PD(MAX) = (TJ(MAX) − TA) / θJA
Connect a 0.1μF low ESR ceramic capacitor between the
BOOT and SW pins. This capacitor provides the gate driver
voltage for the high side MOSFET. It is recommended to
add an external bootstrap diode between an external 5V
and the BOOT pin for efficiency improvement when input
voltage is lower than 5.5V or duty ratio is higher than 65%.
The bootstrap diode can be a low cost one such as 1N4148
or BAT54. The external 5V can be a 5V fixed input from
system or a 5V output of the RT7231/32/33/34. Note that
the external boot voltage must be lower than 5.5V
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
TSSOP-14 (Exposed Pad) package, the thermal
resistance, θJA, is 40°C/W on a standard JEDEC 51-7
four-layer thermal test board. For WDFN-10L3x3 package,
the thermal resistance, θJA, is 60°C/W on a standard
JEDEC 51-7 four-layer thermal test board. For SOP-8
(Exposed Pad) package, the thermal resistance, θJA, is
46°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formulas :
5V
BOOT
RT7231/32/33/34
0.1µF
SW
PD(MAX) = (125°C − 25°C) / (40°C/W) = 2.50W for
TSSOP-14 (Exposed Pad) package
Figure 5. External Bootstrap Diode
PVCC Capacitor Selection
PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.67W for
WDFN-10L 3x3 package
Decouple with a 1μF ceramic capacitor. X7R or X5R grade
dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
PD(MAX) = (125°C − 25°C) / (46°C/W) = 2.174W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curves in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Over Current Protection
When the output shorts to ground, the inductor current
decays very slowly during a single switching cycle. An
over current detector is used to monitor inductor current
to prevent current runaway. The over current detector
monitors the voltage between SW and GND during the
low side MOS turn-on state. This is cycle-by-cycle
protection.
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14
DS7231/32/33/34-09 October 2016
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
