RT6224A/B
2.0
1.6
1.2
0.8
0.4
0.0
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
Four-Layer PCB
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a TSOT-
23-6 (FC) package, the thermal resistance, θJA, is 70°C/
W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum PowerDissipation
Layout Considerations
For best performance of the RT6224A/B, the following
layout guidelines must be strictly followed.
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for a
TSOT-23-6 (FC) package.
Input capacitor must be placed as close to the IC as
possible.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 7 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
SW should be connected to inductor by wide and short
trace. Keep sensitive components away from this trace.
SW should be connected to inductor by Wide and
short trace. Keep sensitive components away from
this trace. Suggestion layout trace wider for thermal.
C
OUT
V
OUT
Keep sensitive components away
from this trace. Suggestion layout
trace wider for thermal.
C
OUT
GND
SW
C
S*
R
S*
Suggestion layout trace
wider for thermal.
BOOT
GND
FB
6
5
4
SW
VIN
EN
C
C
IN
IN
2
3
R
EN
V
IN
Input capacitor must be placed as close
to the IC as possible. Suggestion layout
trace wider for thermal.
V
OUT
R1
R2
The R component must
EN
The feedback components must be
connected as close to the device as
possible.
be connected to V
Suggestion layout trace
wider for thermal.
.
IN
Figure 8. PCB Layout Guide
Copyright 2018 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
www.richtek.com
14
DS6224A/B-02 August 2018
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
