RT6224A/B
Output Capacitor Selection
But some modern digital loads can exhibit nearly
instantaneous load changes and the following section
shows how to calculate the worst-case voltage swings in
response to very fast load steps.
The RT6224A/B is optimized for ceramic output capacitors
and best performance will be obtained using them. The
total output capacitance value is usually determined by
the desired output voltage ripple level and transient response
requirements for sag (undershoot on positive load steps)
and soar (overshoot on negative load steps).
The output voltage transient undershoot and overshoot each
have two components : the voltage steps caused by the
output capacitor's ESR, and the voltage sag and soar due
to the finite output capacitance and the inductor current
slew rate. Use the following formulas to check if the ESR
is low enough (typically not a problem with ceramic
capacitors) and the output capacitance is large enough to
prevent excessive sag and soar on very fast load step
edges, with the chosen inductor value.
Output Ripple
Output ripple at the switching frequency is caused by the
inductor current ripple and its effect on the output
capacitor's ESR and stored charge. These two ripple
components are called ESR ripple and capacitive ripple.
Since ceramic capacitors have extremely low ESR and
relatively little capacitance, both components are similar
in amplitude and both should be considered if ripple is
The amplitude of the ESR step up or down is a function of
the load step and the ESR of the output capacitor :
VESR _STEP = ΔIOUT x RESR
critical.
VRIPPLE = VRIPPLE(ESR) VRIPPLE(C)
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle. The maximum duty cycle during a fast transient
is a function of the on-time and the minimum off-time since
the ACOTTM control scheme will ramp the current using
on-times spaced apart with minimum off-times, which is
as fast as allowed. Calculate the approximate on-time
(neglecting parasitics) and maximum duty cycle for a given
input and output voltage as :
VRIPPLE(ESR) = IL RESR
IL
8COUT fSW
VRIPPLE(C)
=
For the Typical Operating Circuit for 1.2V output and an
inductor ripple of 0.9A, with 22μF output capacitance each
with about 5mΩ ESR including PCB trace resistance, the
output voltage ripple components are :
V
= 0.9A5m = 4.5mV
RIPPLE(ESR)
0.9A
822μF500kHz
V
=
= 10.2mV
RIPPLE(C)
VOUT
IN fSW
tON
tON
=
and DMAX =
V
tON tOFF(MIN)
V
= 4.5mV 10.2mV = 14.7mV
RIPPLE
The actual on-time will be slightly longer as the IC
compensates for voltage drops in the circuit, but we can
neglect both of these since the on-time increase
compensates for the voltage losses. Calculate the output
Output Transient Undershoot and Overshoot
In addition to voltage ripple at the switching frequency,
the output capacitor and its ESR also affect the voltage
sag (undershoot) and soar (overshoot) when the load steps
up and down abruptly. TheACOTTM transient response is
very quick and output transients are usually small.
voltage sag as :
2
L(I
)
OUT
V
SAG
=
2C
V
D
V
MAX OUT
OUT
IN(MIN)
The amplitude of the capacitive soar is a function of the
However, the combination of small ceramic output
capacitors (with little capacitance), low output voltages
(with little stored charge in the output capacitors), and
low duty cycle applications (which require high inductance
to get reasonable ripple currents with high input voltages)
increases the size of voltage variations in response to
very quick load changes. Typically, load changes occur
slowly with respect to the IC's 500kHz switching frequency.
load step, the output capacitor value, the inductor value
and the output voltage :
2
L(I
)
OUT
V
SOAR
=
2C
V
OUT
OUT
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6224A/B-02 August 2018
www.richtek.com
11
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
